Handouts

Course handouts will be available here.

Types of VHDL Code

VHDL Examples

Exercise Problems

These two sets of problems cover material for the final exam.

Problems to prepare for the Midterm, ps

More problems, ps

VHDL FSM and Outputs Examples

I have included both code and the report that shows what memory elements were inferred. The reports were generated using Design Compiler from Synopsys, but I believe the same front end was used in FPGA Express. The report shows the type of element, number of bits and other things like reset and set inputs.

In the Bad version, an extra register is generated for oOutput. The assumption is that this is not what was desired.

In the Good version, the selection of the output value is taken out of the if statement with the clock. Note that the sensitivity list now includes more items. For potentially better simulation efficiency, the combinational logic that is determining the value for oOutput could be put in a separate process. This would reduce the need for simulating the FSM part of the process, such as the case where iX or iY changes.

• Bad Version, Report
• Good Version, Report