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ECE532S: Digital Hardware

Spring 2004

The main course web page is on CCNET at http://courses.ece.utoronto.ca/20041/ece532h1s.

Course Description

Practical applications of advanced digital design concepts. The course is focused around significant projects to be implemented on FPGAs. Topics will include design with embedded processors, FPGAs and ASICs. Labs and projects will be implemented on the Xilinx Multimedia board.

A special thanks to Xilinx for the donations that made these labs possible.

This page is used to provide supplementary information and links. Other course information can be found on the CCNET course page.

Things to Know

Checking Disk Quotas: To check your current disk space usage and limits on the ugsparcs, use the command ``quota -v''.
Directory and File Names: Do not have any directories or filenames in your path that have spaces in them. For example, do not have your project directory in the folder called ``My Documents''. To be safe, it would also be wise to take the same precaution when installing the tools.

About the Lab Hardware

High-level specs on the Multimedia board we are using

Multimedia Board Examples from Xilinx

Multimedia Board User Guide

This is the manual for the board describing the features and pinouts.

Errata: Table 1-14: ZBT RAM BANK3

(original) MEMORY_BANK3_ADDR4 AF4

(should be) MEMORY_BANK3_ADDR4 AF3

Multimedia Board Schematics

The schematics for the Multimedia board.

Multimedia Board File

This file describes some of the connections we use on the board. It should be unzipped in the right place:

EDK_install_dir\board\Xilinx\boards

Datasheet for ZBT memory on the board

Documentation for the EDK Tools and the Processor

Xilinx EDK Documentation: This is the source for the latest documentation on the Xilinx web site for the EDK tools.
Xilinx EDK Document Directory Index: This is the top of documentation directory tree from the EDK installation.
Xilinx EDK Documents: Directly to the documents in the above document tree. Many are also linked below.
EST Tools Guide (2,462,898 bytes)
MicroBlaze Processor Reference Guide (2,211,599 bytes)
Processor IP Reference Guide (2,736,242 bytes): The internal document links may not work depending on how your browser works. Acrobat must run within the browser, not as a separate helper, but this is not always enough.
Xilinx Device Drivers Documentation (6829184 bytes)
GDB GUI Interface: This is a guide to the gdb GUI used in the EDK tools. It has a link to the gdb manual.
Training Lecture (2,944,785 bytes): These are the slides used for the Xilinx EDK workshop at UofT.

Documentation for some of the IP we use in the labs

OPB GPIO Data Sheet (640562 bytes)
OPB Timer/Counter Data Sheet (744595 bytes)
OPB Interrupt Controller Data Sheet (980010 bytes)
OPB Ethernet Controller Data Sheet (18062 bytes)
xemac_intr_fifo_example.c

HDL Simulation using ModelSim

The ModelSim simulator is available on the ugsparcs and eecg research machines. The Xilinx libraries have been installed. You may use this for your Verilog/VHDL simulations.

Getting Started

You will need to set up some environment variables. On the ugsparcs you should:

% source /thesis1/modelsim-5.7f.SUN/CSHRC

or on the eecg research machines

% source /mentor/modelsim-5.7f/CSHRC

and possibly add it to your .cshrc or equivalent to set your path automatically on startup.

You can then start the simulator:

% vsim

which will pop up a welcome window as well as the tool. Hit the Jumpstart button and then Open Documentation. This will pop up an Acrobat reader that links to many documents. There is a link to a Tutorial that can get you started.

A Quicker Start

Including how to include the Xilinx libraries.

Demos and Tours

This takes you to ModelTech's tour page.

FPGA Info

Virtex-II Data Sheets: This is the Xilinx web page for the Virtex-II data sheets. You should have a look through Module 2. In particular, pay attention to the Configurable Logic and the 18K Block SelectRAM sections.
Stratix Data Sheets: This is the Altera web page for the Stratix data sheets. You should have a look through Volume 1, Chapter 2. In particular, look at the sections on the Logic Array Blocks, the Logic Elements and the TriMatrix Memory.

Lecture References

Timing Analysis: High-Speed Digital System Design: A Handbook of Interconnect Theory and Design Practices, Hall, Hall and McCall, Wiley. Chapter 8 is most directly relevant to the lectures. Chapter 9 gets more into setting up spreadsheets to do the computations. Available through UofT library online
Clock Domains and Synchronization: Digital Systems Engineering, Dally and Poulton, Cambridge. Chapter 10.
Synthesis and Scripting Techniques for Designing Multi-Asynchronous Clock Designs, Clifford E. Cummings, SNUG-2001.