This page is used to provide supplementary information and links that
mostly support the lab material.
Other course information, mainly administrative and announcements, can
be found on the CCNET
course page.
To check your current disk space usage and limits on the ugsparcs, use
the command ``quota -v''.
Directory and File Names
Do not have any directories or filenames in your path that have spaces
in them.
For example, do not have your project directory in the folder called
``My Documents''.
To be safe, it would also be wise to take the same precaution when
installing the tools.
This is a site dedicated to the EDK tools and the Multimedia board.
Labs/tutorials and other useful documentation for the tools and
hardware used in this course are available here.
For Spring 2005, we will be using the 6.3 version of the Xilinx tools.
This is the Xilinx web page for the Virtex-II data sheets.
You should have a look through Module 2.
In particular, pay attention to
the Configurable Logic and the 18K Block SelectRAM sections.
This is the Altera web page for the Stratix data sheets.
You should have a look through Volume 1, Chapter 2.
In particular, look at the sections on the Logic Array Blocks, the
Logic Elements and the TriMatrix Memory.
High-Speed Digital System Design: A
Handbook of Interconnect Theory and Design Practices, Hall, Hall
and McCall, Wiley. Chapter 8 is most directly relevant to the
lectures. Chapter 9 gets more into setting up spreadsheets to do
the computations. Available through UofT library
online
Clock Domains and Synchronization
Digital Systems Engineering, Dally and Poulton,
Cambridge. Chapter 10.
