This page is used to provide most of the information and links that
mainly support the lab material.
Blackboard will only be used for announcements, the discussion board,
and content that needs password access, like marks.
A special thanks to
for the donations of hardware
and software that make the labs possible.
Multi-project idea from Professor Mann
A cool idea for some projects proposed by Professor Mann can
be seen here.
I see two reasonable projects that can be done.
Based on what I know has been done in the past, the Vision and
graphics module can be done as one project and the audio as another.
It is okay to have multiple groups work on each part.
We will discuss how to build these components in a way that they can
To check your current disk space usage and limits on the ug machines, use
the command quota -s.
Directory and File Names
Do not have any directories or filenames in your path that have spaces
For example, do not have your project directory in the folder called
To be safe, it would also be wise to take the same precaution when
installing the tools.
512 MB DIMM Memory Errors
If you have a board with 512 MB DIMMs, you will need to make some
changes to avoid read errors.
Find the fix
This is the Xilinx web page for the Virtex-II Pro data sheets.
You should have a look through Module 2.
In particular, pay attention to
the Configurable Logic and the 18K Block SelectRAM sections.
Note that the basic Virtex-II and Virtex-II Pro logic block and memory
architectures are pretty much the same. The Virtex-II Pro
comes with added features, such as the embedded Power PC.
This is the Altera web page for the Stratix data sheets, which is a
similar generation device to the Virtex-II and Virtex-II Pro devices.
You should have a look through Volume 1, Chapter 2.
In particular, look at the sections on the Logic Array Blocks, the
Logic Elements and the TriMatrix Memory.
High-Speed Digital System Design: A
Handbook of Interconnect Theory and Design Practices, Hall, Hall
and McCall, Wiley. Chapter 8 is most directly relevant to the
lectures. Chapter 9 gets more into setting up spreadsheets to do
the computations. Available through UofT library
Clock Domains and Synchronization
Digital Systems Engineering, Dally and Poulton,
Cambridge. Chapter 10.