ECE1373S: VLSI Systems Design

Paul Chow

Spring 2003

Notes and Handouts

• Pins to Verilog flow
• FPGA Design and Verification flow
• Custom and ASIC flows
• Sample directory structure
• VHDL Slides by Sean Peng
• progress.tex, progress.ps
• 505 Registers or Bust, a paper by Wilson Snyder
• Synthesis and Scripting Techniques for Designing Multi-Asynchronous Clock Designs, a paper by Cliff Cummings
• Requirements and Report Format, report.tex

TestBuilder

• Home Page
• Use TestBuilder Classic
• Review of TestBuilder

VHDL Assignment: Point me to your source code by Feb. 3, 2003

Design and simulate a serial booth encoding multipler. It accepts two 16-bit parallel inputs and generates the 32-bit product using booth encoding of the multiplier. The output is a 32-bit parallel value. You will use only one adder/subtractor (and no multiplier!) as the arithmetic element in your circuit.

Estimate the gate count in terms of flip flops and logic.

Percolation

• Algorithm in Word Format Star Office mangles this a bit.
• Algorithm in Star Office Format
• Source Code

Molecular Dynamics (MD)

• Recommended reference: M.P. Allen nd D.J. Tildsley, Computer Simulation of Liquids, Oxford University Press.
  • Chapters 1 and 3 are the starting point.
  • 1987 hardcover version out of print - UofT library has two copies
  • 1989 paperback is available at Amazon.ca
  • Source code for examples in book
    • Velocity version of Verlet Algorithm
• Another code example in Fortran
• Another code example in C

• MD Primer Sections 1-3.5 are adequate for our purposes. Includes some sample code.