ECE1373S: VLSI Systems Design

Paul Chow

Spring 2004

HDL Examples

• Behavioural VHDL For a purely behavioural model.
• OK RTL VHDL Should synthesize to a reasonable circuit.
• Structural VHDL A Synopsys netlist of the adder resulting from synthesis of the above circuit.
• Bad VHDL for Synthesis This will not synthesize!
• Mealy FSM in Verilog Verilog example of a FSM that should synthesize okay.
• Moore FSM in Verilog Another Verilog example of a FSM that should synthesize okay.

Notes and Handouts

• VHDL Slides by Sean Peng
• Pins to Verilog flow
• FPGA Design and Verification flow
• Custom and ASIC flows
• Sample directory structure
• progress.tex, progress.ps
• 505 Registers or Bust, a paper by Wilson Snyder
• Synthesis and Scripting Techniques for Designing Multi-Asynchronous Clock Designs, a paper by Cliff Cummings
• Requirements and Report Format, report.tex

TestBuilder

• Home Page
• Use TestBuilder Classic

HDL Assignment: Point me to your source code by Jan. 27, 2004

Using your best RTL HDL coding style, write a Verilog or VHDL program that implements the following function:

The input, call it WORDIN, receives a stream of 21 parallel data bits. Defining the bits starting from the MSB:

The MSB indicates whether the word is Instruction/Data. It is set to 1 if it is an instruction, 0 if data.

Data Word Format

The data word represents $N \times 2^E$.

MSB

0 designating a data word

Scaling ($E$)

4 bits, indicates a scaling factor of 0-7 left shifts, assume the MSB is always 0.

Data ($N$)

16 bit, 2's complement integer.

Instruction Word Format

MSB

1 designating an instruction word

Instruction

4 bits

Count

If Instruction is Start then this field is the number of data words being added, else the field is ignored.

Instructions

0101

START, remaining 16 bits is the number of data words

1010

STOP, end of data words, remaining bits ignored

0000

NOP, do nothing

The task is to sum all of the input data words, accounting for the scaling factors. The start of a new set of data is a START instruction ended by a STOP instruction. Any NOP instructions are to be ignored. You should check that the number of data words received up to the STOP instruction matches the number given in the START instruction.

There is also a CLK input. WORDIN is valid at the rising edge of CLK.

The main output is called SUMOUT, which is 28 bits long. SUMOUT shows the last valid SUM.

The VALIDSUM output bit is an output that is high for one clock cycle when SUMOUT is changed.

If an error has occurred, like an illegal instruction, there is an output, called ERROR, that should be set high until the next valid SUM is generated.

if an overflow has occurred, the OVR output should be set high until the next valid SUM is generated.

What to do

1. Write and simulate your code so that it works
2. If you can, try to synthesize with any tool of your choice.
3. Estimate the gate count in terms of flip flops and logic before you do any synthesis and see how close you come.
4. You can submit your code by pointing me to a directory on eecg or sending it to me if you are not on eecg.