ECE1373S: Digital Design for Systems-on-Chip

Paul Chow

Spring 2012

About the Course

An advanced digital hardware course dealing with the design of large digital systems implemented using FPGA and ASIC technologies. Topics include architecture design, design flows, HDL design, clocking and interfacing. Prerequisite: Background in digital design using Verilog/VHDL.

Handouts

• 505 Registers or Bust, a paper by Wilson Snyder
• Synthesis and Scripting Techniques for Designing Multi-Asynchronous Clock Designs, a paper by Cliff Cummings
• Requirements and Report Format, report.tex

HDL Examples

• Behavioural VHDL For a purely behavioural model.
• OK RTL VHDL Should synthesize to a reasonable circuit.
• Structural VHDL A Synopsys netlist of the adder resulting from synthesis of the above circuit.
• Bad VHDL for Synthesis This will not synthesize!
• Mealy FSM in Verilog Verilog example of a FSM that should synthesize okay.
• Moore FSM in Verilog Another Verilog example of a FSM that should synthesize okay.
• Design Example This is a simple example illustrating good design practices. You should study it and emulate it!