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High Performance Architectures

This work is about making general-purpose processors better, focusing primarily on microprocessor technology.

My first work in this area was as one of the principals in the design of the MIPS-X RISC microprocessor [1,2,3,4,5,6,7]. For a brief period in time (months!), it was the world's fastest reported microprocessor. A complete description of the processor, including circuits and VLSI layout, is given in a book [8]. This book also includes a brief overview of the software system and a bibliography of some other related publications.

A simple overview of RISC technology is available [9].

Previous work was done in cooperation with Norm Jouppi at DEC Western Research Labs now part of HP Labs. As microprocessors get faster and faster, it is getting harder and harder to get instructions and data out of the main memory in time for execution. This work deals with how various aspects of the memory system interact with the way that instructions are issued [10,11,12,13,14]

The most recent work has been done in cooperation with researchers at the Intel Microprocessor Research Labs where Tor Aamodt has spent time as an intern looking at Prescient Instruction Prefetching [15], which can be used to spawn helper threads for multithreaded architectures.

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Mark Horowitz and Paul Chow.
The MIPS-X Microprocessor.
In Wescon/85, Professional Program Session Record 6, pages 1-6, San Francisco, CA, November 1985. IEEE.

Paul Chow and Mark Horowitz.
Architectural Tradeoffs in the Design of MIPS-X.
In The 14th Annual International Symposium on Computer Architecture, pages 300-308, Pittsburg, Pennsylvania, June 1987. IEEE.
This article also appears in William Stallings, Reduced Instruction Set Computers, 2nd Edition, IEEE Computer Society Press Tutorial, 1990, pp. 230-238.

Mark Horowitz, John Hennessy, Paul Chow, Glenn Gulak, John Acken, Anant Agarwal, Chorng-Yeung Chu, Scott McFarling, Steven Przybylski, Steve Richardson, Arturo Salz, Richard Simoni, Don Stark, Peter Steenkiste, Steve Tjiang, and Malcolm Wing.
A 32b Microprocessor with On-Chip 2Kbyte Instruction Cache.
In ISSCC Digest of Technical Papers, pages 30-31, 328, February 1987.

Mark Horowitz, Paul Chow, Don Stark, Richard Simoni, Arturo Salz, Steven Przybylski, John Hennessy, Glenn Gulak, Anant Agarwal, and John Acken.
MIPS-X: A 20 MIPS Peak, 32-Bit Microprocessor with On-Chip Cache.
IEEE Journal of Solid-State Circuits, SC-22(5):790-799, October 1987.

Paul Chow.
MIPS-X Instruction Set and Programmer's Manual.
Technical Report CSL-86-289, Computer Systems Laboratory, Stanford University, May 1986.
91 pages, paper.pdf (1609728) .

Arturo Salz, Anant Agarwal, and Paul Chow.
MIPS-X: The External Interface.
Technical Report CSL-TR-87-339, Stanford University, Computer Systems Laboratory, November 1987.
34 pages. An updated version appears as Chapter 7 in The MIPS-X RISC Microprocessor, edited by Paul Chow, Kluwer Academic Publishers, 1989.

Paul Chow and Mark Horowitz.
The Design and Testing of MIPS-X.
In Fifth MIT Conference on Advanced Research in VLSI, pages 95-114, MIT, Cambridge, MA, March 1988.

Paul Chow, editor.
The MIPS-X RISC Microprocessor.
Kluwer Academic Publishers, 1989.
ISBN 0-7923-9045-8.

Paul Chow.
Reduced Instruction Set Computers.
IEEE Potentials, pages 28-31, October 1991.
paper.pdf (527378) .

Keith I. Farkas, Norman P. Jouppi, and Paul Chow.
How Useful are Non-blocking Loads, Stream Buffers, and Speculative Execution in Multiple Issue Processors?
In First International Symposium on High-Performance Computer Architecture, pages 78-89. IEEE/ACM, January 1995.
Also available as WRL Research Report 94/8. paper.pdf (850409), Report 94/8 .

Keith I. Farkas, Norman P. Jouppi, and Paul Chow.
Register File Design Configurations in Dynamically Scheduled Processors.
In The 2nd International Symposium on High-Performance Computer Architecture, pages 40-51. IEEE, February 1996.
Also available as WRL Research Report 95/10. (449232), (86453), paper.pdf (125672), Report 95/10 .

Keith I. Farkas, Paul Chow, Norman P. Jouppi, and Zvonko Vranesic.
Memory-System Design Considerations for Dynamically-Scheduled Processors.
In The 24th Annual International Symposium on Computer Architecture, pages 133-143. IEEE/ACM, June 1997.
An extended version is available as WRL Research Report 97/1. (684713), (98279), paper.pdf (160092), Report 97/1 .

Keith Farkas, Paul Chow, Norman Jouppi, and Zvonko Vranesic.
The Multicluster Architecture: Reducing Cycle Time Through Partitioning.
In The 30th Annual International Symposium on Microarchitecture: MICRO-30, pages 149-159, Research Triangle Park, NC, December 1997. IEEE Computer Society/ACM. (250303), (60557), paper.pdf (92066) .

Keith Istvan Farkas.
Memory-system Design Considerations for Dynamically-Scheduled Microprocessors.
PhD thesis, University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, 1997. (3086589), (551790) .

Tor Aamodt, Pedro Marcuello, Paul Chow, Antonio Gonzalez, Per Hammarlund, Hong Wang, and John P. Shen.
A Framework for Modeling and Optimization of Prescient Instruction Prefetch.
In SIGMETRICS '03, pages 13-24. ACM, June 2003.
paper.pdf (444790) .

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Paul Chow 2005-01-02