Up: DSP Processor Design at
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Michael Takefman.
Improving the Performance of a DSP Microprocessor Architecture.
Master's thesis, University of Toronto, Department of Electrical
Engineering, Toronto, Ontario, M5S 3G4, 1990.
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Michael Takefman and Paul Chow.
A Streamlined DSP Microprocessor Architecture.
In International Conference on Acoustics, Speech, and Signal
Processing, pages 1257-1260, Toronto, May 1991. IEEE.
paper.pdf
(571448)
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Vijaya Singh.
An Optimizing C Compiler for a General Purpose DSP Architecture.
Master's thesis, University of Toronto, Department of Electrical
Engineering, Toronto, Ontario, M5S 3G4, 1992.
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Mazen Saghir.
Architectural and Compiler Support for DSP Applications.
Master's thesis, University of Toronto, Department of Electrical and
Computer Engineering, Toronto, Ontario, M5S 3G4, 1993.
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Mazen A.R. Saghir, Paul Chow, and Corinna G. Lee.
Towards Better DSP Architectures and Compilers.
In The Fifth International Conference on Signal Processing
Applications and Technology, ICSPAT'94, pages 658-664, Dallas, Texas,
October 1994.
paper.ps.gz
(35626), .
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Sanjay Pujare, Corinna G. Lee, and Paul Chow.
Machine-Independent Compiler Optimizations for the UofT DSP
Architecture.
In The Sixth International Conference on Signal Processing
Applications and Technology, ICSPAT'95, pages 860-865, Boston, MA, October
1995.
paper.ps.gz
(30726)
.
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Mazen A.R. Saghir, Paul Chow, and Corinna G. Lee.
Application-Driven Design of DSP Architectures and Compilers.
In 1994 International Conference on Acoustics, Speech, and
Signal Processing, pages II-437-II-440, Adelaide, Australia, April 1994.
IEEE.
paper.pdf
(347876)
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Wen-Yen Lin, Corinna G. Lee, and Paul Chow.
An Optimizing Compiler for the TMS320C25 DSP Chip.
In The Fifth International Conference on Signal Processing
Applications and Technology, ICSPAT'94, pages 689-694, Dallas, Texas,
October 1994.
paper.ps.gz
(29185), .
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Mazen A.R. Saghir, Paul Chow, and Corinna G. Lee.
Automatic Data Partitioning for HLL DSP Compilers.
In The Sixth International Conference on Signal Processing
Applications and Technology, ICSPAT'95, pages 866-871, Boston, MA, October
1995.
paper.ps.gz
(28838)
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Mazen A.R. Saghir, Paul Chow, and Corinna G. Lee.
Exploiting Dual Memory Banks in Digital Signal Processors.
In 1996 SIGARCH Conference on Architectural Support for
Programming Languages and Operating Systems (ASPLOS VII), pages 234-243,
Boston, MA, October 1996.
paper.ps.gz
(54915)
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Mark G. Stoodley and Corinna G. Lee.
Software Pipelining Loops with Conditional Branches.
In Micro-29, The 29th Annual IEEE/ACM International Symposium on
Microarchitecture, pages 262-273, Paris, France, December 1996.
Copy available at.
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Mazen A. R. Saghir, Paul Chow, and Corinna G. Lee.
A Comparison of Traditional and VLIW DSP Architectures for Compiled
DSP Applications.
In International Workshop on Compiler and Architecture Support
for Embedded Computing Systems-CASES'98, December 1998.
5 pages. paper.ps.gz
(26100), slides.ps.gz
(34271)
.
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Mazen A.R. Saghir.
Application-Specific Instruction-Set Architectures for Embedded
DSP Applications.
PhD thesis, University of Toronto, Department of Electrical and
Computer Engineering, Toronto, Ontario, M5S 3G4, 1998.
thesis.ps.gz
(362850)
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Sean Peng.
A VLIW Programmable DSP Processor.
Presented at the Symposium on Microelectronics Research &
Development in Canada (MR&DCAN'99), June 1999.
This presentation was awarded the Canadian Microelectronics
Corporation (CMC) International Travel Award (CMC Award) of $2000.
slides.pdf
(1232396)
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Paul Chow
2005-01-02