Author: Roman Genov, JHU this is a web page for the course at http://bach.ece.jhu.edu/roman/page1/courses/490_2001/490_2001.html it contains some of Cadence FAQs from this and previous year's classes as well as from my experience. - How to use a three terminal symbols for NMOS and PMOS transistors with bulk terminal connected to the appropriate power supplies? Often most of the transistors in a design have bulk connected to the most negative supply (for NMOS) or to the most positive (for PMOS). In order to simplify circuit diagrams you can choose to use three-terminal symbols for MOS transistors. They are defined in analogLib library as cells: nmos and pmos (not nmos4 and pmos4). By default their bulk is set to be connected to a source. To change this performe the following: In CIW window go to Tools/CDF/Edit Enter analogLib for Library Name and nmos for Cell Name. Change bulk connection variable string from S to gnd! (for NMOS) vdd! (for PMOS). This will update all instances of cells nmos and pmos. - How do I move a library to a different directory and change the path of the library? One way to do it is to copy your library to a temporary library with a new name. Then delete the old library and coppy thetemporary library back. When coping you'll be asked for the path for the library created: choose the path needed. - How do I set up MOS transistors properties so that I enter w and l in terms of lambda and software calculates metric values for w and l? You need to use Component Description Format (CDF). In CIW window go to Tolls/CDF/Edit Assume the library is mosis05 and the cell is nmos3 - enter these names in and click Apply. CDF edit description contains several levels: Base, User and Effective. In base (not effective!!!) level add two new parameters: w_lambda and l_lambda. Set them to be of integer type with appropriate default values and define callback as mos05(). Move them towards the top of the form so that you can access it easily. The object properties from that you can edit when you make an instance of nmos3 cell in your design will look exactly the same as the CDF edit form you've created. Now, you need to load the file containing this procedure. In CIW window type: load("mosis05.il") The file mosis05.il looks like this: jfet: /depthome/roman/cadence/libs/mosis05>more mosis05.il procedure( mos05() lambda = 0.35e-6 w_lambda = (cdfgData -> w_lambda -> value) l_lambda = (cdfgData -> l_lambda -> value) minl = 2 maxl = 100 minw = 3 maxw = 6000 when((w_lambda < minw || w_lambda > maxw) printf("Width out of range. Setting to default.") w_lambda = minw) when((l_lambda < minl || l_lambda > maxl) printf("Length out of range. Setting to default.") l_lambda = minl) cdfgData -> w_lambda -> value = w_lambda cdfgData -> w -> value = sprintf(s "%g" w_lambda*lambda) cdfgData -> l_lambda -> value = l_lambda cdfgData -> l -> value = sprintf(s "%g" l_lambda*lambda) ) Now changing the parameters w_lambda and l_lambda will trigger (by using the call back mos05())appropriate changes in w and l (in this case accordingly to HP05 design rules: lambda=0.35) For more information look at CDF user guide in OpenBook - comes up when you click on help from CDF edit window. - Often you need to obtain some parameters from your techfile to use in a callback procedure (like mos05() - the one described above). For this you need first to create a variable pointing to a techfile attached to the current library "mosis05": tf = techGetTechFile(ddGetObj("mosis05") Then you can read appropriate attributes or properties from the techfile. For example to get ordered spacing (i.e. enclosure), spacing(i.e. min width, min spacing): ;Techfile Parameters for device parameter extraction unless( diff_contEnc = techGetOrderedSpacingRule(tf "minEnclosure" "diff" "cont") printf("diff_contEnc not in techfile")) unless( contSz = techGetSpacingRule(tf "minWidth" "cont") printf("contSz not in techfile")) unless( poly_contSp = techGetSpacingRule(tf "minSpacing" "poly1" "cont") printf("poly_contSp not in techfile")) For more examples to search in OpenBook for techGetTechFile and choose the first item found. - How to calculate Drain and Source area and perimeter and display them in Edit Object Properties window? Implement SKILL language code similar to the following: sd_area = (w_lambda * (contSz + poly_contSp + diff_contEnc)) * lambda * lambda sd_perim = (2*w_lambda + 2*(contSz + poly_contSp + diff_contEnc)) * lambda cdfgData -> w_lambda -> value = w_lambda cdfgData -> w -> value = sprintf(nil,"%g", w_lambda*lambda) cdfgData -> l_lambda -> value = l_lambda cdfgData -> l -> value = sprintf(nil,"%g", l_lambda*lambda) cdfgData -> fingers -> value = fingers cdfgData -> cascode -> value = cascode cdfgData -> bulk -> value = bulk cdfgData -> ps -> value = sprintf(nil, "%g", sd_perim) cdfgData -> pd -> value = sprintf(nil, "%g", sd_perim) cdfgData -> as -> value = sprintf(nil, "%g", sd_area) cdfgData -> ad -> value = sprintf(nil, "%g", sd_area) - A complete CDF callback procedure for NMOS transistors in HP0.5 technology. It calculates metric w and l, checks if they are in limits, updates bulk, fingers and cascode variables, and calculates Drain and Source area and perimeter: jfet: /depthome/roman/cadence/libs/mosis05>more mosis05.il.o* procedure( mos05() tf = techGetTechFile(ddGetObj("mosis05")) ;Techfile Parameters for device parameter extraction unless( diff_contEnc = techGetOrderedSpacingRule(tf "minEnclosure" "diff" "cont") printf("diff_contEnc not in techfile")) unless( contSz = techGetSpacingRule(tf "minWidth" "cont") printf("contSz not in techfile")) unless( poly_contSp = techGetSpacingRule(tf "minSpacing" "poly1" "cont") printf("poly_contSp not in techfile")) lambda = 0.35e-6 w_lambda = (cdfgData -> w_lambda -> value) l_lambda = (cdfgData -> l_lambda -> value) bulk = (cdfgData -> bulk -> value) fingers = (cdfgData -> fingers -> value) cascode = (cdfgData -> cascode -> value) minl = techGetSpacingRule(tf "minWidth" "poly1") maxl = 100 minw = 3 maxw = 6000 when((w_lambda < minw || w_lambda > maxw) printf("Width out of range. Setting to default.") w_lambda = minw) when((l_lambda < minl || l_lambda > maxl) printf("Length out of range. Setting to default.") l_lambda = minl) sd_area = (w_lambda * (contSz + poly_contSp + diff_contEnc)) * lambda * lambda sd_perim = (2*w_lambda + 2*(contSz + poly_contSp + diff_contEnc)) * lambda cdfgData -> w_lambda -> value = w_lambda cdfgData -> w -> value = sprintf(nil,"%g", w_lambda*lambda) cdfgData -> l_lambda -> value = l_lambda cdfgData -> l -> value = sprintf(nil,"%g", l_lambda*lambda) cdfgData -> fingers -> value = fingers cdfgData -> cascode -> value = cascode cdfgData -> bulk -> value = bulk cdfgData -> ps -> value = sprintf(nil, "%g", sd_perim) cdfgData -> pd -> value = sprintf(nil, "%g", sd_perim) cdfgData -> as -> value = sprintf(nil, "%g", sd_area) cdfgData -> ad -> value = sprintf(nil, "%g", sd_area) ) - How are the default parameters for parameters in Edit Object Properties window can be initialized? One way to do this is to specify an initialization procedure in formInitProc field i n CDF Edit window, base type CDF. We call it setDefaults and define it in mosis05.il : procedure( setDefaults(cdfDataId) mos05() ) All it does is every time a cell is created it calls mos05() procedure (see above) a nd updates all of the default parameters specified in mos05(). - How do I make sure that the labels displayed in the schematic editor window are updated when a InitProc is called (let's say when you select a device and click "q") To achieve this you need to perform the following assignment: cdfgForm -> cdfModified = t I chose to put it into InitProc itself: procedure( setDefaults(cdfDataId) cdfgForm -> cdfModified = t ; this makes the schematic editor update ; on every formInitProc call !!! mos05() ; this calls mos05() - to set all parameters ; on the cell initialization ) Now whenever you bring up edit component parameters window and exit it the displayed parameters will be updated accordingly. - How to deal with working with two different setups: Jeremy's and new, Ralph's? I decided to have library mosis05 for the first one and hp05 for the second one. 1. I left to deal with mosis05 for later. Some of the files that might be helpful for this: /depthome/roman/cadence/libs/mosis05_jeremy - the mosis05_jeremy library (from clsp account) has: mosis05.tf - techfiles that defines the layer map plus some devices such as Poly contact, etc. divaDRC.rul divaERC.rul divaEXT.rul divaLVS.rul - rules files pcell - to create handy layout cells /depthome/roman/clsp/roman/cadence - my old clsp account; /depthome/roman/clsp/hek/cadence - kai's copies of jeremy's files; /depthome/roman/cadence/libs/mosis05 - my first efforts to recreate this library on new server. 2. The hp05 library is intended to use all of the new techfiles and some old SKILL language scripts to help with simulation/layout. - How to print from Cadence on sun stations in Barton 120 to a laser printer? First save the waveforms or schematic as a .ps file. Then use: lp -dhp4000tn_1 - How do I use a new technology file with an existing design library? You need to load (CIW/ Tech File/Load) the technology file (i.e. /classapps/Cadence/techfiles/mosis.tf) into a technology library (i.e. hp05). Then attach this tech library (CIW/Tech File/Attach) to youdesign library (i.e. SVM) - How to double check that your techfiles are correct? It might be a good idea to export your design as .CIF and then read it in into magic and use their tech files to double check DRC, etc. Magic techfiles are at http://www.mosis.org/Technical/Designsupport/mag-files.html (for numerous processes). - How to have w and l of a MOS transistor be set up to be displayed when you start up a new session? in a schematic window of a cell for a given library go to /Edit/label Display chose parameter; library; parameter; then click on a device and select w_lambda, l_lambda, none (non selected). Now click on attach and then also save (to labelDisplay.il) then do the same for the complementary device at the end go to CIW/Options/Save Defaults with "merge" option selected. The set up will be added to ~/.cdsenv - how to have a cell (i.e. nSwitch) with a parameter (i.e. width) defined in the top view and source by the lowerlevel circuit (NMOS transistor) as a parameter? define a string type parameter w_lambda (parse as number, do not use units) in CDF base description of your cell "nSwitch". Then in w field for NMOS device type pPar("w_lambda"). - How to import a CIF file to Cadence? First, create a layer map file. A working version of such a file is shown below (/depthome/roman/cadence/cif2cadence): padtext drawing XP Nwell drawing CWN Active drawing CAA Pselect drawing CSP Nselect drawing CSN Poly1 drawing CPG ;cont drawing CCC P1Con drawing CCP P2Con drawing CCE ActX drawing CCA Metal1 drawing CMF Via drawing CVA Metal2 drawing CMS Glass drawing COG Poly2 drawing CEL Via2 drawing CVS Metal3 drawing CMT ;ccd drawing CCD Pbase drawing CBA text drawing2 CX CapWell drawing CWC SiBlock drawing CSB Then from CIW window do: file/import/cif/ user-defined data: specify the name of the layer map table file (above) Specify input file name and library to import it to. CIF files include only metric (centimicron) information. To scale your design to a 1lambda-1micron internal unit representation, enter a scaling factor in the UU/DBU field (0.01 by default - also, need to set tot this value whenever you export a cif file) according to the following equation: UU/DBU = 0.0100000*2u/current_design_lambda Click apply and check file PIPO.log to check the log for the import procedure. If the layout is not on the grid, you can reduce the spacing of the grid to the smallest distance the layout is off by, move the whole layout to a convenient larger spacing grid and change the grid spacing back to a bigger one. - Example: how to import a 1.2u technology CIF file. If you follow the procedure above, you'll end up with UU/DBU=0.01*2/1.2=0.01666667. This will cause the round off error which will shift the layout of grid. There's a way to get around it. The idea is to edit .CIF file (using L-edit) so that the scaling ratio in each DS line is dividable by 3. Let's say all of the cells in your .CIF file have cell definition statements as: DS 30 2 (I had this for kenanacq.cif chip) To check that all of the cells have the same scaling coefficient do: grep -c DS kenanacq.cif grep -c '30 2;' kenanacq.cif the two output numbers should match. So the multiplier is 30/2=15 and dividable by 3. Then you do: subst '30 2;' '1 1;' kenanacq.cif (copy it to a different file first) Now your UU/DBU=0.01*2/1.2*15=0.25 which is a nice rational number !!! What is left to mention is how to manage L-edit to have multiplier be 30/2. For this you need to play with Internal Unit and Lambda definitions. For reference look in the file 1.2_conversion. - How to read CIF (Caltech Intermediate FOrmat) files: (from "Computer Aids for VLSI Design" by S. Rubin) Caltech Intermediate Format (CIF) is a recent form for the description of integrated circuits. Created by the university community, CIF has provided a common database structure for the integration of many research tools. CIF provides a limited set of graphics primitives that are useful for describing the two-dimensional shapes on the different layers of a chip. The format allows hierarchical description, which makes the representation concise. In addition, it is a terse but human-readable text format. CIF is therefore a concise and powerful descriptive form for VLSI geometry. Each statement in CIF consists of a keyword or letter followed by parameters and terminated with a semicolon. Spaces must separate the parameters but there are no restrictions on the number of statements per line or of the particular columns of any field. Comments can be inserted anywhere by enclosing them in parenthesis. There are only a few CIF statements and they fall into one of two categories: geometry or control. The geometry statements are: LAYER to switch mask layers, BOX to draw a rectangle, WIRE to draw a path, ROUNDFLASH to draw a circle, POLYGON to draw an arbitrary figure, and CALL to draw a subroutine of other geometry statements. The control statements are DS to start the definition of a subroutine, DF to finish the definition of a subroutine, DD to delete the definition of subroutines, 0 through 9 to include additional user-specified information, and END to terminate a CIF file. All of these keywords are usually abbreviated to one or two letters that are unique. FOr more information, look at cif_tutorial.html or at http://www.rulabinsky.com/cavd/text/chapb.html - How to search for the next match of a quiery in Open Book? The pull-down menu says !nn - that is press ESP and twice n - How to translate L-Edit labels into valid labels in Cadence? Labels created in L-edit are assigned the same layer name as the layer they point to. In Cadence when doing DRC this flags a problem when dubiousData function is running. To assign all contacts the layer name "text" the following perl script can be used: #!/usr/local/bin/perl # This script substitutes any CIF layer type in a line that defines # a label (starts with 94) with a layer'text' defined in CIF as CX # This avoids DRC error messages in Cadence when divaDRC.rul runs # dubiousData command if($ARGV[0] eq '') {printf "\nUsage: label_le2cds \n\n"; exit();}; $file_name = shift @ARGV; $count = 0; open(IN, "$file_name") || die "Can't open $file_name: $!\n"; open(OUT, ">subst__temp") || die "Can't open subst__temp: $!\n"; while($line = ) { if($line =~ /^94 /) { ($label_code, $label_name, $coord, $cifLbl) = split(/ /, $line); #printf"cifLbl: $cifLbl\n"; $cifLbl = 'CX'; print OUT ("94 ",$label_name," ",$coord," ",$cifLbl,";\n"); $count = $count + 1; } else { print OUT $line; } } close IN; close OUT; rename(subst__temp, $file_name); printf "$count labels are substituted to layer type text in $file_name\n"; Or look at label_le2cds To count the number of labels, use grep -c '^94 ' temp In order to edit labels, in LSW window go to /Edit/Set valid layers - lick on text layer. We can now also create pins from labels in Virtuoso Editing - Create Pins from Labels - How to simulated extracted layouts with a top view being schematic? In Analog Artist window you need to go to /setup/Environment and under "Switch View List" add "extracted" before "schematic". This way the simulator with netlist extracted view instead of schematic. - Example of above: extracted NPN transistor simulation. Lay out a NPN transistor as in MOSIS design rules. Extract it using the extract file: /depthome/roman/cadence/techfiles/divaEXT_no_NPNarea.rul (it has (attachParasitic ScaledEA "area" NPN) line commented out - this line extracts the area of the emitter - which MOSIS NPN models didn't simulate right with). Now edit CDF description of analogLib cell npn - in effective view add model - npn. Include model in your model file: * From MOSIS: look at ~roman/projects/kenanacq/npn_mosis .MODEL npn bjt type=npn + BF=82 IS=7.943E-17 NF=9.9063E-01 NE=1.3893 VAF=71.4 + IKF=1.025E-02 ISE=8.268E-17 RE=17.4 RC=752.42 RB=1.213E+03 + RBM=13.08 ISC=1.643E-15 NC=1.0266 + CJE=0.0976E-12 MJE=0.5050 VJE=0.85 CJC=0.0981E-12 MJC=0.4990 VJC=0.80 + CJS=0.1800E-12 MJS=0.2033 VJS=0.70 * AREA OF TRANSISTOR * AE=64 um^2 PE=32 um AB=336 um^2 PB=80 um AC=1536 um^2 PC=160 um In Analog Artist window under setup/environment add the model file: /depthome/roman/cadence/models/AMI15/bsim3v3.1/tt.inc In Analog Artist window under setup/model path delete any path that is there. In Analog Artist window you need to go to /setup/Environment and under "Switch View List" a dd "extracted" before "schematic". This way the simulator with netlist extracted view inste ad of schematic. Create a sumbol view of your npn cell with pins matching to the ones in the extracted cell view (make sure it doesn't have a model field in its CDF). Apply appropriate test voltage sources. You are ready to simulate. You can also set up Setup/Environment/Netlist type as flat - than you can easily see extracted netlist in the appropriate simulation directory (i.e. ~roman/simulation/npn_test_extr/spectreS/schematic/netlist/raw/npn_test_extr). - How to extract Poly1 resistors from layout? Apply layer Resistor on the top (exactly matching!) of Poly1 where it is a resistor. The following code implements resistance computation: FOR AMI1.2: ; POLY-SIBLOCK RESISTOR (extractDevice PolySBRes (PolySBResTap "PLUS" "MINUS") "res symbol" ) (PolyResArea = (measureParameter area (PolySBRes) )) (PolyResLen = (measureParameter length (PolySBRes coincident Poly1) 0.5 ;In layout the edges of Poly1 )) ; and Resistor have to coincide!!! ; We need 0.5 above because we measure two edges (PolyResLeff = (calculateParameter ; subtract out deltaL (PolyResLen - 0/0.6) ; here it's = 0 )) (PolyResSquare = (calculateParameter ( (PolyResLeff * PolyResLeff) / PolyResArea) )) (PolyRes = (calculateParameter (PolyResSquare * 23.4) ; used to be 110 - I changed to 23.4 )) (saveParameter PolyRes "r") (saveRecognition PolySBRes "Resistor") - How to extract an MOS capacitor with one diffusion terminal? 1. In LSW window under Edit/Set Valid Layers enable a new layer pin, drawing 2. place two pieces of that layer on the diffusion terminal so that they do not touch eachover and they are coincident, but not overlapping the gate. 3. Put Capacitor, dg layer over the gate. 4. In layer.il define a layer ; Edited 12/30/99 to allow D and S extraction for A NMOSCAP ; with only one diffusion terminal. Use layer pin (which can be enabled ; from LSW/Edit/Layer Tap) to draw D & S terminals. (pin = (geomOr "pin")) (NMOSCAPpin = (geomAnd NSD pin)) and connect it: (geomConnect (via pin NMOSCAPpin NSD) ; Edited R. Genov - for 3 terminal MOSCAP (G&S together) ... ) 5. In divaEXT.rul file define extraction procedure: ;Edited by R. Genov: ; 12/26/99 - created a 4-terminal MOSCAP devices which is ; extracted as a MOS transistor - allows to have D/S at different potential ; than B (need for SVM A/D cell) ; Here we don't compute length as an average of two side-lengths. Instead ; we measure width, area, and then divide the secondby the first. That way ; we preserve the exact capacitance of the gate to the inversion channel. ; NMOSCAP, PMOSCAP FOR ALL Only NMOS implemented!!! ; Created a new layer - NMOSCAPpin overlap ov Active1 aND PIN layer. By drawing two ;pieces of pin layer and defining physical option, we are able to extract both S and D ;as connected pins (while having only one active terminal). (extractDevice NMoscap (Poly1wire "G") (NMOSCAPpin "S" "D") (Pwell "B") "nmos4 symbol" physical ) (saveInterconnect (NMOSCAPpin "Nselect") ) - If Cadence crashed because of network problems you might find out that the next time you log in. Some off your cells are read-only. How to fix this? 1. exit cadence 2. do ps -el | grep cdsd (that's lock deamon) 3. if such a process exists, kill it with -9 option. 4. restart cadence - Global nets: an ! sign at the end of a pin/net base name makes it global - To use Vituoso Layout Synthesizer, in Virtuoso window go to Tools and select layout synthesis.