Several Ph.D. and M.S. level graduate assistantships are available in the area of Intelligent Sensory Integrated Systems Design. Such systems comprise analog and digital VLSI circuits that acquire sensory data, perform adaptive computation and implement convenient user interface. The research projects range from mixed-signal VLSI circuits and systems for sensory information processing, and high- performance adaptive computing to autonomous microelectronic systems design. The focus is on developing high-throughput, high integration density and low-power integrated sensory systems that are tailored for implementations on mobile portable platforms and can learn from the environment and adapt to it.
For up-to-date information on these and other
research projects contact Prof. Roman Genov at roman@eecg.toronto.edu The
following research assistantship projects are anticipated starting
in the Fall or Summer of 2004 :
The objective of this research is to develop miniature portable video acquisition and processing systems that can be trained to detect a wide range of visual events of interest and communicate this information to a base station, while operating autonomously for extended periods of time. The mobile units function solely or in clusters and are connected through a wireless radio network. Training can be performed off-line or incrementally in run-time. These ``intelligent sensors'' will be implemented in a mixed-signal VLSI CMOS technology, will have a life-time of several weeks or months while powered by a coin-type battery, and will be conveniently small-size and low-weight allowing for access anywhere and anytime.
The approach to creating a micropower miniature trainable object detection and identification system, is the one that integrates image sensors, adaptive signal processing, and wireless (RF) networking on the same substrate. Visual stimuli will be acquired by an active pixel image sensor with integrated in-sensor video pre-processing. Object detection will be carried out by a mixed-signal VLSI pattern recognition processor. A powerful learning paradigm, the support vector machine (SVM), will be implemented on-chip for off-line and on-line learning and classification. Low-power transceiver will provide a wireless interface on event-driven basis. The focus of this research is on implementing learning paradigms on silicon through algorithm development, circuit design and system integration.
The focus of this research is on investigation and development of an image acquisition module within the ``intelligent image sensor'' framework. An active pixel sensor with focal plane video pre-processing will be designed and integrated with an energy-efficient pattern recognition processor. The prototype will perform variable resolution imaging to allow for scale-variant object detection, motion estimation to eliminate redundancy in computation and visual feature extraction for robust classifier performance.
While signal processing power consumption continues to decline approximately as the forth power of feature size, radiated energy required to reliably transmit a signal over a given distance dominates wireless systems power costs. Distributed intelligent sensors (see above) life-time is extended by transmitting only the information of interest. A low-power low average bit rate transmitter will be developed for this purpose. A low-power receiver will be integrated to allow for dynamic remote reconfiguration. Both transmitter and receiver will be implemented in a standard CMOS technology.
Recently it has been shown that a simple learning paradigm, the support vector machine (SVM), outperforms some of the most elaborately tuned expert systems and neural networks in object recognition tasks. In run-time, the SVM operates by computing a kernel-based distance between the object's vector at the input and a set of prototype templates (support vectors) selected from the training set, and weighting the results to produce the oracle at the output.
A massively parallel, fine-grain distributed architecture for real-time kernel-based pattern recognition and its efficient implementation in mixed-signal VLSI technology has been developed in our lab. At the core of the externally digital architecture is a high-density, low-power analog array performing binary-binary matrix-vector multiplication, as the elementary operation in computing inner-product based kernels between presented input and stored support vectors. The three-transistor unit cell in the analog array combines a charge injection device (CID) binary multiplier and analog accumulator with embedded dynamic random-access memory (DRAM). High output resolution is achieved with low complexity quantizers by oversampling in the input binary representation combined with delta-sigma modulated quantization at the output. This research has resulted in the Kerneltron, the first support vector "machine" in silicon. It features 256 inputs and 128 templates, delivering over 1 trillion (10^12) multiply-accumulates-per-second for every Watt of power at 8-bit output resolution. Such computational efficiency and integration density exceed that of most available digital processors by several orders of magnitude each. These advantages allow us to implement real-time pattern recognition systems on an inexpensive miniature platform integrating image sensors, adaptive processing and wireless interface. This research project will focus on large-scale VLSI implementation of unabridged SVM architecture. Multiple Kerneltron computational arrays will be tiled together in a single architecture to allow for detection of objects of higher complexity. The architecture will be extended to include wavelet-based feature extraction for robust large-margin classification. Buffering and reorganization of sensory input data, as well as programmable SVM decision rule parameters and the choice of kernel function will be implemented on-chip.