The Edward S. Rogers Sr.

Department of Electrical and Computer Engineering

10 King's College Road

Toronto, Ontario M5S 3G4 Canada

URL: http://www.eecg.utoronto.ca/~roman

Email: roman@eecg.utoronto.ca

Phone: (416) 946-8666

Fax: (416) 971-2286

RESEARCH INTERESTS

Analog and digital VLSI circuits, systems and algorithms for energy-efficient signal processing with applications to electrical, chemical and photonic sensory information acquisition, biosensor arrays, neural interfaces, parallel signal processing, adaptive computing, and implantable and wearable biomedical electronics.

EDUCATION

The Johns Hopkins University, Ph.D., Electrical and Computer Engineering, Baltimore, MD, 08/2002.

Dissertation: Massively Parallel Mixed-Signal VLSI Kernel Machines.

Advisor: Gert Cauwenberghs

Massachusetts Institute of Technology, Visiting Student, AI Lab/CBCL, Cambridge, MA, 1/99-8/99.

The Johns Hopkins University, M.S.E., Electrical and Computer Engineering, Baltimore, MD, 1998.

GPA 4.00/4.00

Rochester Institute of Technology, B.S., Electrical Engineering, Rochester, NY, 1996.

GPA 4.00/4.00

ACADEMIC AND INDUSTRIAL POSITIONS

University of Toronto, Toronto, ON, 7/2008-Present.

Associate Professor, Electronics Group, Department of Electrical and Computer Engineering.

University of Toronto, Toronto, ON, 9/2002-6/2008.

Assistant Professor, Electronics Group, Department of Electrical and Computer Engineering.

The Johns Hopkins University, Baltimore, MD, 9/96-8/2002.

Research Assistant, Adaptive Microsystems Lab, Department of Electrical and Computer Engineering.

Swiss Federal Institute of Technology (EPFL), Lausanne, Switzerland, 6/98-7/98.

Visiting Researcher, Autonomous Systems Lab.

Xerox Corporation, Webster, NY, 3/96-8/96.    

Design Engineer CO-OP, Advanced Development Team in the Color Imaging Systems Division.

Atmel Corporation, Columbia, MD, 6/95-12/95.

Design Engineer Intern, Chesapeake Design Center.

AWARDS AND HONORS

Best Student Paper, IEEE Int. Symp. on Circuits and Systems (with A. Nilchi, top 9 student papers, ~1000 regular papers), 2009.

Best Student Paper, IEEE Int. Symp. on Circuits and Systems (with F. Shahrokhi, top 9 student papers, ~1000 regular papers), 2009.

Best Paper, IEEE Int. Symp. on Circuits and Systems (with A. Nilchi, top 6 papers, nominated by Sensory Systems Technical Committee), 2009.

Brian L. Barge Award for Excellence in Microsystems Integration (with M. Jafari, $3,500 prize), 2008.

DALSA Corporation Componentware/CAD Award (with A. Olyaei, $3,000 prize), 2006.

Canadian Institutes of Health Research (CIHR)/BioContact Next Generation Award (with M. Derchansky and two others, $2,000 prize), 2005.

RESEARCH GRANTS AND CONTRACTS                                                                 Annual            Total

Short-term contract, PI, Industrial Partner, 2/2008-3/2008.

“Electro-Optical Microsystem for DNA Detection,” PI, Ontario Centres of Excellence, Centre for Photonics, 1/2008-9/2008.

“2-D Integrated Microsystem for Neural Recording and Stimulation in the Brain,” peer-reviewed Hybrid Integration project, PI, Canadian Microelectronics Corporation, 12/2007-9/2008.

 “Integrated Neural Interfaces for Epileptic Seizure Monitoring“, Co-I, subcontract from Prof. P. Carlen, University Health Network, University of Toronto, 9/2006-8/2008.

“Hybrid Integration Technologies for Optical DNA Detection,“ peer-reviewed Hybrid Integration project, PI, Canadian Microelectronics Corporation, 1/2008-12/2008.

 “Smart Sensory Microsystems,” PI, Natural Sciences and Engineering Council of Canada (NSERC), Discovery Award, 05/2007-04/2012.

NSERC Industrial Postgraduate Scholarship (recipient: M.A.Sc. student Farzaneh Shahrokhi), Medtrode Corporation, 9/2006-8/2008.

“Hybrid Integration Technologies for Brain-Chip Interfaces,“ Hybrid Integration project, PI, Canadian Microelectronics Corporation, 2006.

Infrastructure Operating Fund Award, PI, Canada Foundation for Innovation (CFI), 4/2006-3/2010.

“Intelligent Sensory Integrated Systems,” PI, New Opportunities Award, Canada Foundation for Innovation (CFI), 11/2005-3/2008.

“Intelligent Sensory Integrated Systems,” PI, Ontario Research Fund, 11/2005-3/2008.

“Real-time Human Gate Recognition for Automated Surveillance,” Co-I with D. Hatzinakos, K. Plataniotis, and P. Klentrou, Communications and Information Technology Ontario (CITO), 6/2004-5/2006.

“Autonomous Integrated Vision Systems,” PI, Natural Sciences and Engineering Council of Canada (NSERC), Discovery Award, 05/2003-04/2007.

“Mixed-Signal VLSI Circuits and Systems,” PI, Connaught Foundation, 10/2002.

“Mixed-Signal VLSI Circuits and Systems,” PI, University of Toronto, ECE Dept., 10/2002.

$13,250

$22,500

$6,000

$7,517

$33,408

$33,408

$17,225

$20,850

Total:

$10,000

$25,000

$8,000

$26,500

$14,000

$112,500

$12,000

$5,000

$30,068

$100,226

$100,226

$34,450

$83,400

$10,000

$100,000

$671,370

GRADUATE RESEARCH ADVISEES

Ashkan Olyaei, M.A.Sc. Degree, 09/2003-04/2006.

Thesis: ‘ViPro: Focal-Plane CMOS Spatially-Oversampling Computational Image Sensor’

Grade: A+

Currently at: Marvell Semiconductor, San Jose, CA

Rafal Karakiewicz, M.A.Sc. Degree, 09/2003-08/2006.

Thesis: Mixed-Signal VLSI Adiabatic Array Computing

Grade: A+

Currently at: Synopsis Corporation, Toronto, ON

Joseph Aziz, M.A.Sc. Degree, 09/2004-10/2006 (co-supervised with Prof. B. Bardakjian).

Thesis: Multi-Channel Signal-Processing Integrated Neural Interfaces

Grade: A+

Currently at: Broadcom Corporation, Singapore

Alireza Nilchi, M.A.Sc. Degree, 09/2005-11/2007.

Thesis: Focal-Plane CMOS Algorithmically-Multiplying Computational Image Sensor

Grade: A+                                                     

Currently: University of Toronto, Electronics Group, Candidate for Ph.D. Degree

Meisam Nazari, M.A.Sc. Degree, 01/2006-06/2008.

Thesis: CMOS Wide-Dynamic-Range High-Throughput Potentiostat

Grade: A+

Currently: California Institute of Technology, Candidate for Ph.D. Degree

Ritu Raj Singh, M.A.Sc. Degree, 09/2006-11/2008.

Thesis: Luminescence Contact Imaging Microsystems

Grade: A+

Currently: Granite SemiCom Corporation

Farzaneh Shahrokhi, M.A.Sc. Degree, 09/2006-01/2009.

Thesis: Multi-Channel Fully Differential Digital Integrated Neural Recording and Stimulation Interfaces

Grade: A+

Ruslana Gelman, Candidate for M.A.Sc. Degree, 09/2006-current (co-supervised with Prof. P. Carlen).

Derek Ho, Candidate for Ph.D. Degree, 09/2007-current (co-supervised with Prof. G. Gulak).

Karim Abdelhalim, Candidate for Ph.D. Degree, 09/2007-current.

Hamed Jafari, Candidate for Ph.D. Degree, 09/2007-current.

Shan He, Candidate for M.A.Sc. Degree, 09/2008-current.

UNDERGRADUATE DESIGN PROJECT AND THESIS ADVISEES

2003-2004

2004-2005

2005-2006

2006-2007

2007-2008

2008-2009

King Sun (Francis) Tam

T.K. Chan

Po-Yu Liu

Mustafa Alam

Ahmad Attia

Ajmal Khan

Taha Sheikh

Houman Akbari

Negar Habibi

Yasaman Faghih

John Tan

Colin Li

Chuan Qin

Ruslana Gelman

Angie Mehta

Khaled Qasmieh

Khalil Oudah

Tina Tahmoures-Zadeh

Jon Perras

Natasha Baker

Brian Choi

David Wu

Kim Liu

Eric Pai

Ryan Payogo

Fady Akladios

Benny Tu

David Crockett

Vadim Smolyakov

(design project)

(design project)

(design project)

(design project)

(design project)

(design project)

(design project)

(design project)

(design project)

(design project)

(design project, co-supervised with Prof. B. Bardakjian)

(design project, co-supervised with Prof. B. Bardakjian)

(design project, co-supervised with Prof. B. Bardakjian)

(design project)

(design project)

(design project)

(design project)

(design project)

(undergraduate thesis)

(design project)

(design project)

(design project)

(design project)

(design project)

(design project)

(design project)

(design project)

(design project)

(undergraduate thesis)

UNDERGRADUATE SUMMER RESEARCH ADVISEES

2004

2005

2006

Alborz Jooyaie

John Tan

Hsiang-Hua (Andy) Hung

Ruslana Gelman

Jasper Chan

Gaurav Jain

Stephen Chin

Khalil Oudah

(NSERC summer student)

(NSERC summer student)

(NSERC summer student)

(NSERC summer student)

(NSERC summer student)

(NSERC summer student)

(NSERC summer student)

(summer student)

TEACHING

“VLSI Design Methodology,” ECE1388 9/2004-12/2004 (26 graduate students), 9/2005-12/2005 (16 graduate students), 9/2006-12/2006 (13 graduate students), 9/2007-12/2007 (25 graduate students), 9/2008-12/2008 (13 graduate students).

“Analog Electronics,” ECE530 1/2004-4/2004 (55 students), 1/2005-4/2005 (65 students), 1/2006-4/2006 (89 students), 1/2007-4/2007 (66 students), 1/2008-4/2008 (44 students), 1/2009-4/2009 (54 students).

“Introductory Electronics,” ECE231 1/2003-4/2003 (89 students), 1/2004-4/2004 (87 students), 1/2005-4/2005 (88 students), 1/2006-4/2006 (70 students), 1/2007-4/2007 (60 students), 1/2008-4/2008 (107 students),  1/2009-4/2009 (103 students; 320 students coordinated).

“Selected Topics in Circuits and Systems – VLSI Circuits and Systems for Pattern Recognition,” ECE1390 9/2003-12/2003 (5 graduate students).

SHORT COURSES/TUTORIALS

“Pattern Recognition at 1GOPS/mW and Beyond: Massively Parallel Mixed-Signal VLSI Storage, Computing and Data Conversion,” Microelectronics Strategic Alliance of Quebec (ReSMiQ), half-day intensive course, Montreal, QC, March 4, 2005.

INVITED PRESENTATIONS

“Electro-Chemical Integrated Neural Interfaces,” National Research Council (NRC) of Canada, Neurochip Development Initiative - Strategic Meeting, Invited Talk, November, 2006.

 “Electro-Chemical Integrated Neural Interfaces,” National Research Council (NRC) of Canada, Institute for Biological Sciences, Invited Seminar, October, 2006.

“Kerneltron: Massively Parallel Mixed-Signal VLSI Pattern Recognition Processor,” Centre for Vision Research, York University, Toronto, ON, March 11, 2005.

 “Kerneltron: Massively Parallel Mixed-Signal VLSI Pattern Recognition Processor,” IEEE EDS/CAS Western New York Conference, Invited Plenary Talk, Rochester, NY, Nov. 3, 2004.

“A 1GMACS/mW Mixed-Signal Differential-Charge CID/DRAM Processor,” IEEE Int. Conf. on Circuits and Systems for Communications (ICCSC’04), Invited Plenary Talk, Moscow, Russia, June 30 - July 2, 2004.

“Kerneltron: Massively Parallel Mixed-Signal VLSI Pattern Recognition Processor,” Invited Seminar, Rochester Institute of Technology, Rochester, NY, Apr. 30, 2004.

 “Kerneltron: Support Vector ‘Machine’ in Silicon,” VLSI Seminar Series, School of Electrical and Computer Engineering, Cornell University, Ithaca, NY, Nov.13, 2003.

PROFESSIONAL ACTIVITIES

Associate Editor:

IEEE Transactions on Biomedical Circuits and Systems (2006-present).

IEEE Signal Processing Letters (2008-present).

External Advisory Board Member: Department of Electrical Engineering, Rochester Institute of Technology, 2004-current.

Panel Member: National Sciences and Engineering Research Council of Canada (NSERC) Strategic Projects Selection Panel, 2008-2009.

Technical Program Co-Chair: IEEE Biomedical Circuits and Systems Conference (BioCAS’2007).

Organizer/Co-organizer: “Integrated Neural Interfaces,” Special Invited Session (ISCAS’2006); “Integrated Neural Implants,” Special Invited Session (ISCAS’2007); “Electrochemical Sensory Microsystems,” Special Invited Session (BioCAS’2007).

International Liaison: IEEE 4^th International Symposium on Electronic Design, Test and Applications 2008.

Society Membership:

Institute of Electrical and Electronic Engineers (IEEE),

Circuits and Systems (CAS) Society,

Solid-State Circuits (SSC) Society,

Engineering in Medicine and Biology (EMB) Society.

Technical Committee Membership:

Analog Signal Processing TC of IEEE CAS Society,

Neural Systems and Applications TC of IEEE CAS Society,

Biomedical Circuits and Systems TC of IEEE CAS Society,

Sensory Systems TC of IEEE CAS Society.

Technical Program Committee Membership:

ACM Great Lakes Symposium on VLSI (GLSVLSI’2003).

SPIE Bioengineered and Bioinspired Systems Conference (Bio’2003, 2005).

IEEE 6^th Electro/Information Technology Conference (2006).

IEEE Northeast Workshop on Circuits and Systems (NEWCAS’2006, 2007, 2008, 2009).

IEEE Midwest Symposium on Circuits and Systems (MWSCAS’2007) (joint with NEWCAS’2007).

IEEE Biomedical Circuits and Systems Conference (BioCAS’2007, 2008).

Conference Review Committee Membership:

Review Committee, IEEE Int. Symp. Circuits and Systems (ISCAS’2003-2009).

Conference Track Chair/Co-chair:

IEEE Int. Conf. of the Engineering in Medicine and Biology Society, “Neural Microsystems and Instrumentation” Track Co-chair, (EMBC’2006).

Conference Session Chair/Co-chair:

IEEE Int. Symp. Circuits and Systems, “Self-Correcting ADC,” (ISCAS’2002); “Neural Systems and Applications,” (ISCAS’2004); “Neural Computation,” “Neural Classifiers,” (ISCAS’2005); “Medical Interfacing System,” “Integrated Neural Interfaces” (Special Session), “Switched Capacitor Circuits,” “Analog Filtering & Signal Processing,” (ISCAS'2006); “Integrated Neural Implants,” (Special Session, ISCAS’2007); “Biomedical Circuits and Systems for Neural Recording,” (ISCAS’2009).

IEEE Biomedical Circuits and Systems Conference, “Electrochemical Sensory Microsystems,” (BioCAS’2007); “Bio-Signal Processing,” (BioCAS’2007).

SPIE Int. Symp. Microtechnologies, Bioengineered and Bioinspired Systems 2003, “Biosensors.”

Journal and Conference Reviews:

Journal of Solid-State Circuits (JSSC); IEEE Transactions on Circuits and Systems I&II (TCAS-I&II); IEEE Transactions on Neural Networks (TNN); IEEE Int. Symp. on Circuits and Systems (ISCAS); Great Lakes Symposium on VLSI (GLSVLSI); Neural Information Processing Systems Conference (NIPS).

University/Department Committees Membership:

Awards and Scholarships Committee, Faculty of Applied Science and Engineering (2007-current);

Curriculum Matters Committee, Department of Electrical and Computer Engineering (2005-current);

Graduate Coordinator, Electronics Group, Department of Electrical and Computer Engineering (2008-current).

BOOK CHAPTERS

[BC1] “CMOS Focal-Plane Spatially-Oversampling Computational Image Sensor,” A. Olyaei and R. Genov, in “Circuits at the Nanoscale: Communications, Imaging, and Sensing,” edited by K. Iniewski, CRC Press, 2008.

REFEREED JOURNAL PUBLICATIONS

[J13] “A Fully Differential Multi-Channel CMOS Integrated Potentiostat,” M. Nazari, and R. Genov, subm. IEEE Transactions on Circuits and Systems I: Regular Papers.

[J12] “A 96-Channel CMOS Potentiostat with Dual-Mode Single-Slope ADCs,” M. Nazari, and R. Genov, subm. to IEEE Journal of Solid-State Circuits.

[J11] “On-Silicon Neural Activity Monitoring and Time-Frequency Analysis for Epileptic Seizure Prediction,” J. Aziz, R. Karakiewicz, R. Genov, A. Chiu, B. Bardakjian, M. Derchansky, P. Carlen, resubm. IEEE Transactions on Neural Systems and Rehabilitation Engineering.

[J10] “Focal-Plane Algorithmically-Multiplying CMOS Computational Image Sensor,” A. Nilchi, J. Aziz, and R. Genov, IEEE Journal of Solid-State Circuits, Vol. 44, No. 4, Apr. 2009.

[J9] “256-Channel Neural Recording and Delta Compression Microsystem with 3D Electrodes,” J. Aziz, K. Abdelhalim, R. Shulyzki, R. Genov, B. Bardakjian, M. Derchansky, D. Serletis, P. Carlen, IEEE Journal of Solid-State Circuits, Vol. 44, No. 3, pp. 995-1005, March 2009.

[J8] “480-GMACS/mW Resonant Adiabatic Mixed-Signal Processor Array for Charge-Based Pattern Recognition,” R. Karakiewicz, R. Genov, G. Cauwenberghs, IEEE Journal of Solid-State Circuits, Vol. 42, No. 11, pp. 2573-2584, Nov. 2007.

[J7] “Brain-Silicon Interface for High-Resolution In Vitro Neural Recording,” J. Aziz, R. Genov, B. Bardakjian, M. Derchansky, P. Carlen, IEEE Transactions on Biomedical Circuits and Systems, Vol. 1, No. 1, pp. 56-62, March 2007.

[J6] “Focal-Plane Spatially-Oversampling CMOS Image Compression Sensor,” A. Olyaei and R. Genov, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 54, No. 1, pp. 26-34, Jan. 2007.

[J5] “16-Channel Integrated Potentiostat for Distributed Neurochemical Sensing,” R. Genov, M. Stanacevic, M. Naware, G. Cauwenberghs, N. Thakor, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 53, No. 11, pp. 2371-2376, Nov. 2006.

[J4] “Dynamic MOS Sigmoid Array Folding Analog-to-Digital Conversion,” R. Genov and G. Cauwenberghs, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 51, No. 1, pp. 182-186, Jan. 2004.

[J3] “Silicon Support Vector Machine with On-Line Learning,” R. Genov, S. Chakrabartty, G. Cauwenberghs, International Journal of Pattern Recognition and Artificial Intelligence, Vol. 17, No. 3, pp. 385-404, 2003.

[J2] “Kerneltron: Support Vector ‘Machine’ in Silicon,” R. Genov, G. Cauwenberghs, IEEE Transactions on Neural Networks, Vol. 14, No. 5, pp. 1426-1434, Sept. 2003.

[J1] “Charge-Mode Parallel Architecture for Matrix-Vector Multiplication,” R. Genov, G. Cauwenberghs, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Vol. 48, No. 10, pp. 930-936, Oct. 2001.

REFEREED CONFERENCE AND WORKSHOP PUBLICATIONS

[C34] “CMOS Image Compression Sensor with Algorithmically-Multiplying ADCs,” A. Nilchi, J. Aziz, and R. Genov, IEEE Int. Symp. on Circuits and Systems (ISCAS'2009), May 2009.

[C33] “128-Channel Fully Differential Digital Neural Recording and Stimulation Interface,” F. Shahrokhi, K. Abdelhalim, R. Genov, IEEE Int. Symp. on Circuits and Systems (ISCAS'2009), May 2009.

[C32] “A Hybrid Thin-Film/CMOS Fluorescence Contact Imager,” R. Singh, D. Ho, A. Nilchi, R. Genov and G. Gulak, IEEE Int. Symp. on Circuits and Systems (ISCAS'2009), May 2009.

[C31] “A Fully Differential CMOS Potentiostat,” M. Nazari, R. Genov, IEEE Int. Symp. on Circuits and Systems (ISCAS'2009), May 2009.

[C30] “Multi-Step Binary-Weighted Capacitive Digital-to-Analog Converter Architecture,” R. Singh, R. Genov, R. Kotamraju, B. Mazhari, IEEE Midwest Symposium on Circuits and Systems (MWSCAS’08), Knoxville, Tennessee, Aug. 10-13, 2008.

[C29] “1.1 TMACS/mW Load-Balanced Resonant Charge-Recycling Array Processor,” R. Karakiewicz, R. Genov, G. Cauwenberghs, IEEE Custom Integrated Circuits Conference (CICC’2007), Sept. 2007.

[C28] “In Vitro Epileptic Seizure Prediction Microsystem,” J. Aziz, R. Karakiewicz, R. Genov, A. W. L. Chiu, B. L. Bardakjian, M. Derchansky, P. L. Carlen, IEEE Int. Symp. on Circuits and Systems (ISCAS'2007), May 2007.

[C27] “256-Channel Neural Recording Microsystem with On-Chip 3D Electrodes,” J. Aziz, R. Genov, M. Derchansky, B. Bardakjian, P. Carlen, IEEE International Solid-State Circuits Conference (ISSCC’2007), Feb. 2007.

[C26] “ViPro: Focal-Plane Spatially-Oversampling CMOS Image Compression Sensor,” A. Olyaei, R. Genov, IEEE Custom Integrated Circuits Conference (CICC’2006), Sept. 2006.

[C25] “Towards Real-Time In-Implant Epileptic Seizure Prediction,” J. N. Y. Aziz, R. Karakiewicz, R. Genov, B. L. Bardakjian, M. Derchansky and P. L. Carlen, IEEE Engineering in Medicine and Biology Conference (EMBC’2006), Sept. 2006.

[C24] “175 GMACS/mW Charge-Mode Adiabatic Mixed-Signal Array Processor,” R. Karakiewicz, R. Genov, G. Cauwenberghs, IEEE Symposium on VLSI Circuits, June 2006.

[C23] “Real-Time Seizure Monitoring and Spectral Analysis Microsystem,” J. N. Y. Aziz,  R. Karakiewicz,  R. Genov, B. L. Bardakjian, M. Derchansky, P. L. Carlen, IEEE Int. Symp. on Circuits and Systems (ISCAS'2006), May 2006.

[C22] “256-Channel Integrated Neural Interface and Spatio-Temporal Signal Processor,” J. N. Y. Aziz, R. Genov, B. L. Bardakjian, M. Derchansky, P. L. Carlen, IEEE Int. Symp. on Circuits and Systems (ISCAS'2006), May 2006.

[C21] “Electro-Chemical Multi-Channel Integrated Neural Interface Technologies,” J. N. Y. Aziz, R. Genov, IEEE Int. Symp. on Circuits and Systems (ISCAS'2006), May 2006.

[C20] “Algorithmic Delta-Sigma Modulated FIR Filter,” A. Olyaei, R. Genov, IEEE Int. Symp. on Circuits and Systems (ISCAS'2006), May 2006.

[C19] “Multi-Channel Integrated Neural Interfaces for Distributed Electro-Chemical Sensing,” J. Aziz, R. Genov, IEEE Midwest Symposium on Circuits and Systems (MWSCAS’05), Cincinnati, Ohio, Aug. 7-10, 2005.

[C18] “Focal-Plane CMOS Wavelet Feature Extraction for Real-Time Pattern Recognition,” A. Olyaei, R. Genov, SPIE Photonics North, Toronto, Canada, Sept. 12-14, 2005.

[C17] “Mixed-Signal CMOS Haar Wavelet Compression Imager Architecture,” A. Olyaei, R. Genov, IEEE Midwest Symposium on Circuits and Systems (MWSCAS’05), Cincinnati, Ohio, Aug. 7-10, 2005.

[C16] “Minimal Activity Mixed-Signal VLSI Architecture for Real-Time Linear Transforms in Video,” R. Karakiewicz and R. Genov, IEEE Int. Symp. on Circuits and Systems (ISCAS'2005), Kobe, Japan, May 23-26, 2005.

[C15] “Integrated Multi-Electrode Fluidic Nitric-Oxide Sensor and VLSI Potentiostat Array,” M. Naware, A. Rege, R. Genov, M. Stanacevic, G. Cauwenberghs, N. Thakor, IEEE Int. Symp. on Circuits and Systems (ISCAS'2004), Vancouver, Canada, May 26-29, 2004.

[C14] “VLSI Multi-Channel Track-and-Hold Potentiostat,” R. Genov, M. Stanacevic, M. Naware, G. Cauwenberghs, N. Thakor, in Microtechnologies for the New Millennium, Bioengineered and Bioinspired Systems 2003, Proc. SPIE vol. 5119, May 2003.

[C13] “Algorithmic Partial Analog-to-Digital Conversion in Mixed-Signal Array Processors,” R. Genov, G. Cauwenberghs, Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS'2003), Bangkok, Thailand, May 25-28, 2003.

[C12] “A 5.9mW 6.5GMACS CID/DRAM Array Processor,” R. Genov, G. Cauwenberghs, G. Mulliken, and F. Adil, Proc. IEEE European Solid-State Circuits Conference (ESSCIRC’2002), Florence, Italy, Sept. 24-26, 2002.

[C11] “Kerneltron: Support Vector ‘Machine’ in Silicon,” R. Genov, G. Cauwenberghs, Proc. SVM’2002, Lecture Notes in Computer Science, Niagara Falls, ON, Aug. 10, 2002.

[C10] “Delta-Sigma Algorithmic Analog-to-Digital Conversion,” G. Mulliken, F. Adil, G. Cauwenberghs, and  R. Genov, Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS'2002), Phoenix, AZ, May 26-29, 2002.

[C9] “Charge-Based MOS Correlated Double Sampling Comparator and Folding Circuit,” R. Genov and G. Cauwenberghs, Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS'2002), Phoenix, AZ, May 26-29, 2002.

[C8] “Neuromorphic Processor for Real-Time Biosonar Object Detection ,” G. Cauwenberghs, R. T. Edwards, Y. Deng, R. Genov, and D. Lemonds, Proc. IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP’2002), Orlando, FL, May 13-17, 2002.

[C7] “Stochastic Mixed-Signal VLSI Architecture for High-Dimensional Kernel Machines,” R. Genov, G. Cauwenberghs, Advances in Neural Information Processing Systems (NIPS'2001), Cambridge, MA: MIT Press, vol. 14, 2002.

[C6] “CID/DRAM Mixed-Signal Parallel Distributed Array Processor,” R. Genov, G. Cauwenberghs, IEEE 14th International ASIC/SOC Conference (ASIC/SOC'2001), Washington, DC, Sept. 12-15, 2001.

[C5] “Massively Parallel Inner-Product Array Processor,” R. Genov, G. Cauwenberghs, Proc. of IEEE Int. Joint Conference on Neural Networks (IJCNN'2001), Washington, DC, July 15-19, 2001.

[C4] “Analog Array Processor with Digital Resolution Enhancement and Offset Compensation,” R. Genov, G. Cauwenberghs, Proc. of Conference on Information Sciences and Systems (CISS'2001), Baltimore, MD, March 21-23, 2001.

[C3] “Charge-Mode Parallel Architecture for Matrix-Vector Multiplication,” R. Genov and G. Cauwenberghs, Proc. of 43rd IEEE Midwest Symposium on Circuits and Systems (MWSCAS'2000), Lansing, MI, Aug. 8-11, 2000. (Best Student Paper Award, 3rd place.)

[C2] “Learning to Navigate from Limited Sensory Input: Experiments with the Khepera Microrobot,” R. Genov, S. Madhavapeddi and G. Cauwenberghs, Proc. of IEEE International Joint Conference on Neural Networks (IJCNN'99), Washington, DC, vol. 3, pp. 2061-2064, 1999. (Best Presentation Award.)

[C1] “16-Channel Single-Chip Current-Mode Track-and-Hold Acquisition System with 100 dB Dynamic Range,” R. Genov and G. Cauwenberghs, Proc. of IEEE International Symposium on Circuits and Systems (ISCAS'99), Orlando, FL, vol. 6, pp. 350-353, 1999. (Best Student Paper Contest Finalist.)

UNREFEREED CONFERENCE  AND WORKSHOP PUBLICATIONS

[UC3] “CMOS Wavelet Compression Imager Architecture,” A. Olyaei, R. Genov, IEEE CAS Emerging Technologies Workshop, St. Petersburg, Russia, June 23-24, 2005.

[UC2] “A 1GMACS/mW Mixed-Signal Differential-Charge CID/DRAM Processor,” R. Genov, IEEE Int. Conf. on Circuits and Systems for Communications (ICCSC’2004), Moscow, Russia, June 30 - July 2, 2004 (invited).

[UC1] “Embedded Dynamic Memory and Charge-Mode Logic for Parallel Array Processing,” R. Genov, G. Cauwenberghs, Proc. of the 5th World Multi-Conference on Systemics, Cybernetics and Informatics (SCI'2001), Orlando, FL, July 22-25, 2001.

OTHER PUBLICATIONS

[O1] “Massively Parallel Mixed-Signal VLSI Kernel Machines,” R. Genov, Ph.D. Dissertation, Department of Electrical and Computer Engineering, The Johns Hopkins University, May 2003.

MEDIA ARTICLES

“The Race to Build a Better Brain: A New Computer Chip Pushes the Machine-Human Interface,” D. Hawaleshka, Maclean’s Magazine, Vol. 120, No. 10, March 19, 2007. The article features our work on integrated brain-chip interfaces.

“Pushing the Evolution of the Machine-Human Interface,” Skulematters Alumni Magazine, Fall, 2007. The article features our work on integrated brain-chip interfaces.