The Edward S. Rogers Sr.

Department of Electrical and Computer Engineering

10 King's College Road

Toronto, Ontario M5S 3G4 Canada

URL: http://www.eecg.utoronto.ca/~roman

Email: roman@eecg.utoronto.ca

Phone: (416) 946-8666

Fax: (416) 971-2286

RESEARCH INTERESTS

Analog and digital VLSI circuits, systems and algorithms for energy-efficient signal processing with applications to electrical, chemical and photonic sensory information acquisition, biosensor arrays, neural interfaces, parallel signal processing, adaptive computing, and implantable and wearable biomedical electronics.

EDUCATION

The Johns Hopkins University, Ph.D., Electrical and Computer Engineering, Baltimore, MD, 08/2002.

Dissertation: Massively Parallel Mixed-Signal VLSI Kernel Machines.

Advisor: Gert Cauwenberghs

Massachusetts Institute of Technology, Visiting Student, AI Lab/CBCL, Cambridge, MA, 1/99-8/99.

The Johns Hopkins University, M.S.E., Electrical and Computer Engineering, Baltimore, MD, 1998.

GPA 4.00/4.00

Rochester Institute of Technology, B.S., Electrical Engineering, Rochester, NY, 1996.

GPA 4.00/4.00, Highest Honors, Rank in class – 1/316

PROFESSIONAL EXPERIENCE

University of Toronto, Toronto, ON, 9/2002-Present

Assistant Professor, Electronics Group, Department of Electrical and Computer Engineering.

The Johns Hopkins University, Baltimore, MD, 9/96-8/2002

Research Assistant, Adaptive Microsystems Lab, Electrical and Computer Engineering Department.

Swiss Federal Institute of Technology (EPFL), Lausanne, Switzerland, 6/98-7/98.

Visiting Researcher, Autonomous Systems Lab.

Xerox Corporation, Webster, NY, 3/96-8/96.    

Design Engineer CO-OP, Advanced Development Team in the Color Imaging Systems Division.

Atmel Corporation, Columbia, MD, 6/95-12/95.

Design Engineer Intern, Chesapeake Design Center.

AWARDS AND HONORS

DALSA Corporation Componentware/CAD Award, 2006.

Canadian Microelectronics Corporation (CMC) Microsystems Integration Award runner-up, 2006.

Canadian Institutes of Health Reasearch (CIHR)/BioContact Next Generation Award, 2nd place, 2005.

Best Student Paper Award, 3rd place, IEEE Midwest Symposium on Circuits and Systems, 2000.

Best Presentation Award, IEEE International Joint Conference on Neural Networks, 1999.

Best Student Paper Contest Finalist, IEEE International Symposium on Circuits and Systems, 1999.

RESEARCH GRANTS AND CONTRACTS

“Intelligent Sensory Integrated Systems,” R. Genov (PI), New Opportunities Award, Canadian Foundation for Innovation (CFI), Ministry of Economic Development and Trade (MEDT), and industrial sponsors, $200,226, 06/2004-05/2009.

“Real-time Human Gate Recognition for Automated Surveillance,” D. Hatzinakos, K. Plataniotis, R. Genov (Co-PI), P. Klentrou, Communications and Information Technology Ontario (CITO), $137,800, 6/2004-5/2006.

“Autonomous Integrated Vision Systems,” R. Genov (PI), Natural Sciences and Engineering Council of Canada (NSERC), Discovery Award, $83,400, 05/2003-04/2007.

“Mixed-Signal VLSI Circuits and Systems,” R. Genov (PI), Connaught Foundation, $10,000, 10/2002.

“Mixed-Signal VLSI Circuits and Systems,” R. Genov (PI), University of Toronto, ECE Dept., $100,000, 10/2002.

GRADUATE RESEARCH ADVISEES

Ashkan Olyaei, M.A.Sc. Degree, 04/2006.

Thesis: ‘ViPro: Focal-Plane CMOS Spatially-Oversampling Computational Image Sensor’

Currently at: Marvell Semiconductor, San Jose, CA

Rafal Karakiewicz, M.A.Sc. Degree, 08/2006.

Thesis: Mixed-Signal VLSI Adiabatic Array Computing

Currently at: SNOWBUSH, Toronto, ON

Joseph Aziz, M.A.Sc. Degree, 10/2006 (co-supervised with Prof. Bardakjian).

Thesis: Multi-Channel Signal-Processing Integrated Neural Interfaces

Currently at: Broadcom, Singapore

Alireza Nilchi, Candidate for M.A.Sc. Degree, 09/2005-current.

Meisam Nazari, Candidate for M.A.Sc. Degree, 01/2006-current.

Ruslana Gelman, Candidate for M.A.Sc. Degree, 09/2006-current (co-supervised with Prof. Carlen).

Farzaneh Shahrokhi, Candidate for M.A.Sc. Degree, 09/2006-current.

Rituraj Singh, Candidate for M.A.Sc. Degree, 09/2006-current.

Mohammad Poustinchi, Candidate for M.A.Sc. Degree, 01/2007-current.

TEACHING

“VLSI Design Methodology,” ECE1388 9/2004-12/2004 (26 graduate students), 9/2005-12/2005 (16 graduate students), 9/2006-12/2006 (13 graduate students).

“Analog Electronics,” ECE530 1/2004-4/2004, 1/2005-4/2005,  1/2006-4/2006, 1/2007-4/2007 (55, 65, 89, 66 students).

“Introductory Electronics,” ECE231 1/2003-4/2003, 1/2004-4/2004, 1/2005-4/2005, 1/2006-4/2006, 1/2007-4/2007 (70-100 students).

“Selected Topics in Circuits and Systems – VLSI Circuits and Systems for Pattern Recognition,” ECE1390 9/2003-12/2003 (5 graduate students).

SHORT COURSES/TUTORIALS

“Pattern Recognition at 1GOPS/mW and Beyond: Massively Parallel Mixed-Signal VLSI Storage, Computing and Data Conversion,” Microelectronics Strategic Alliance of Quebec (ReSMiQ), half-day intensive course, Montreal, QC, March 4, 2005.

INVITED PRESENTATIONS

“Electro-Chemical Integrated Neural Interfaces,” National Research Council (NRC) of Canada, Neurochip Development Initiative - Strategic Meeting, Invited Talk, November, 2006.

 “Electro-Chemical Integrated Neural Interfaces,” National Research Council (NRC) of Canada, Institute for Biological Sciences, Invited Seminar, October, 2006.

 “CMOS Wavelet Compression Imager Architecture,” IEEE CAS Emerging Technologies Workshop, St. Petersburg, Russia, June 23-24, Invited Talk, 2005.

“Kerneltron: Massively Parallel Mixed-Signal VLSI Pattern Recognition Processor,” Centre for Vision Research, York University, Toronto, ON, March 11, 2005.

 “Kerneltron: Massively Parallel Mixed-Signal VLSI Pattern Recognition Processor,” IEEE EDS/CAS Western New York Conference, Invited Plenary Talk, Rochester, NY, Nov. 3, 2004.

“A 1GMACS/mW Mixed-Signal Differential-Charge CID/DRAM Processor,” IEEE Int. Conf.  on Circuits and Systems for Communications (ICCSC’04), Invited Plenary Talk,  Moscow, Russia, June 30 - July 2, 2004.

“Kerneltron: Massively Parallel Mixed-Signal VLSI Pattern Recognition Processor,” Invited Seminar, Rochester Institute of Technology, Rochester, NY, Apr. 30, 2004.

“Silicon Support Vector Machine,” Neural Information Processing Systems Conference (NIPS’2003), Demonstrations track presentation, Vancouver, BC, Dec. 10, 2003.

“Kerneltron: Support Vector ‘Machine’ in Silicon,” VLSI Seminar Series, School of Electrical and Computer Engineering, Cornell University, Ithaca, NY, Nov.13, 2003.

 “VLSI Array for Massively Parallel Kernel Computation,” Workshop on Neuromorphic Engineering, Telluride, CO, July 2001.

PROFESSIONAL ACTIVITIES

Associate Editor: IEEE Transactions on Biomedical Circuits and Systems (2006-present).

External Advisory Board Member, Department of Electrical Engineering, Rochester Institute of Technology, 2004-current.

Technical Program Co-Chair: IEEE Biomedical Circuits and Systems Conference (BioCAS’2007).

Organizer/Co-organizer: “Integrated Neural Interfaces,” Special Invited Session (ISCAS’2006), “Integrated Neural Implants,” Special Invited Session (ISCAS’2007).

Society Membership:

Institute of Electrical and Electronic Engineers (IEEE),

Circuits and Systems (CAS) Society,

Solid-State Circuits (SSC) Society,

Engineering in Medicine and Biology (EMB) Society.

Technical Committee Membership:

Analog Signal Processing TC of IEEE CAS Society,

Neural Systems and Applications TC of IEEE CAS Society,

Biomedical Circuits and Systems TC of IEEE CAS Society,

Sensory Systems TC of IEEE CAS Society.

Technical Program Committee Membership:

ACM Great Lakes Symposium on VLSI (GLSVLSI’2003).

SPIE Bioengineered and Bioinspired Systems Conference (Bio’2003, 2005).

IEEE 6^th Electro/Information Technology Conference (2006).

IEEE Northeast Workshop on Circuits and Systems (NEWCAS’2006, 2007).

IEEE Midwest Symposium on Circuits and Systems (MWSCAS’2007) (joint with NEWCAS’2007).

Conference Review Committees:

Review Committee Member, IEEE Int. Symp. Circuits and Systems (ISCAS’2003-2007).

Conference Session/Track Chair/Co-chair:

IEEE Int. Conf. of the Engineering in Medicine and Biology Society, “Neural Microsystems and Instrumentation,” (EMBC’2006).

IEEE Int. Symp. Circuits and Systems, “Self-Correcting ADC,” (ISCAS’2002); “Neural Systems and Applications,” (ISCAS’2004); “Neural Computation,” “Neural Classifiers,” (ISCAS’2005); “Medical Interfacing System,” “Integrated Neural Interfaces” (Special Session), “Switched Capacitor Circuits,” “Analog Filtering & Signal Processing,” (ISCAS'2006);  “Integrated Neural Implants,” (Special Session, ISCAS’2007).

SPIE Int. Symp. Microtechnologies, Bioengineered and Bioinspired Systems 2003, “Biosensors.”

Journal and Conference Reviews:

Journal of Solid-State Circuits (JSSC); IEEE Transactions on Circuits and Systems I&II (TCAS-I&II); IEEE Transactions on Neural Networks (TNN); IEEE Int. Symp. on Circuits and Systems (ISCAS); Great Lakes Symposium on VLSI (GLSVLSI); Neural Information Processing Systems Conference (NIPS).

University/Department Committees: Curriculum Matters Committee (2005-2007).

REFEREED JOURNAL PUBLICATIONS TO BE SUBMITTED

“256-Channel Neural Recording and Delta Compression Microsystem with 3D Electrodes,” J. Aziz, R. Genov, B. Bardakjian, M. Derchansky, P. Carlen, to be subm. IEEE Journal of Solid-State Circuits, 2007.

“An Epileptic Seizure Prediction Microsystem,” J. N. Y. Aziz,  R. Karakiewicz,  R. Genov, A. W. L. Chiu, B. L. Bardakjian, M. Derchansky, P. L. Carlen, to be subm. IEEE Transactions on Neural Systems and Rehabilitation Engineering,” 2007.

“480-GMACS/mW Resonant Adiabatic Charge-Mode Mixed-Signal Array,” R. Karakiewicz, R. Genov, G. Cauwenberghs, subm. IEEE Journal of Solid-State Circuits, 2007.

REFEREED JOURNAL PUBLICATIONS

“Brain-Silicon Interface for High-Resolution In Vitro Neural Recording,” J. Aziz, R. Genov, B. Bardakjian, M. Derchansky, P. Carlen, IEEE Trans. Biomed. Circuits and Systems, 2007.

“Focal-Plane Spatially-Oversampling CMOS Image Compression Sensor,” A. Olyaei, R. Genov, IEEE Trans. Circuits and Systems I: Regular Papers, 2007.

“16-Channel Integrated Potentiostat for Distributed Neurochemical Sensing,” R. Genov, M. Stanacevic, M. Naware, G. Cauwenberghs, N. Thakor, IEEE Trans. Circuits and Systems I: Regular Papers, 2006.

 “Dynamic MOS Sigmoid Array Folding Analog-to-Digital Conversion,” R. Genov and G. Cauwenberghs, IEEE Trans. Circuits and Systems I: Regular Papers, vol. 51 (1), pp. 182-186, 2004.

“Silicon Support Vector Machine with On-Line Learning,” R. Genov, S. Chakrabartty, G. Cauwenberghs, Int. Journal of Pattern Recognition and Artificial Intelligence, vol. 17 (3), pp. 385-404, 2003.

“Kerneltron: Support Vector ‘Machine’ in Silicon,” R. Genov, G. Cauwenberghs, IEEE Trans. on Neural Networks, vol. 14 (5), pp. 1426-1434, Sept. 2003.

“Charge-Mode Parallel Architecture for Matrix-Vector Multiplication,” R. Genov, G. Cauwenberghs, IEEE Trans. on Circuits and Systems II: Analog and Digital Signal Processing, vol. 48 (10), pp. 930-936, Oct. 2001.

REFEREED CONFERENCE  PUBLICATIONS

“In Vitro Epileptic Seizure Prediction Microsystem,” J. Aziz, R. Karakiewicz, R. Genov, A. W. L. Chiu, B. L. Bardakjian, M. Derchansky, P. L. Carlen, IEEE Int. Symp. on Circuits and Systems (ISCAS'2007), 2007.

“256-Channel Neural Recording Microsystem with On-Chip 3D Electrodes,” J. Aziz, R. Genov, M. Derchansky, B. Bardakjian, P. Carlen, IEEE International Solid-State Circuits Conference (ISSCC’2007), 2007.

“ViPro: Focal-Plane Spatially-Oversampling CMOS Image Compression Sensor,” A. Olyaei, R. Genov, IEEE Custom Integrated Circuits Conference (CICC’2006), 2006.

 “Towards Real-Time In-Implant Epileptic Seizure Prediction,” J. N. Y. Aziz, R. Karakiewicz, R. Genov, B. L. Bardakjian, M. Derchansky and P. L. Carlen, IEEE Engineering in Medicine and Biology Conference (EMBC’2006), 2006.

“175 GMACS/mW Charge-Mode Adiabatic Mixed-Signal Array Processor,” R. Karakiewicz, R. Genov, G. Cauwenberghs, IEEE Symposium on VLSI Circuits, 2006.

“Real-Time Seizure Monitoring and Spectral Analysis Microsystem,” J. N. Y. Aziz,  R. Karakiewicz,  R. Genov, B. L. Bardakjian, M. Derchansky, P. L. Carlen, IEEE Int. Symp. on Circuits and Systems (ISCAS'2006), 2006.

“256-Channel Integrated Neural Interface and Spatio-Temporal Signal Processor,” J. N. Y. Aziz, R. Genov, B. L. Bardakjian, M. Derchansky, P. L. Carlen, IEEE Int. Symp. on Circuits and Systems (ISCAS'2006), 2006.

“Electro-Chemical Multi-Channel Integrated Neural Interface Technologies,” J. N. Y. Aziz, R. Genov, IEEE Int. Symp. on Circuits and Systems (ISCAS'2006), 2006.

“Algorithmic Delta-Sigma Modulated FIR Filter,” A. Olyaei, R. Genov, IEEE Int. Symp. on Circuits and Systems (ISCAS'2006), 2006.

 “Multi-Channel Integrated Neural Interfaces for Distributed Electro-Chemical Sensing,” J. Aziz, R. Genov, Midwest Symposium on Circuits and Systems (MWSCAS’05), Cincinnati, Ohio, Aug. 7-10, 2005.

“CMOS Haar Wavelet Sensory Parallel Processor Architecture,” A. Olyaei, R. Genov, SPIE Photonics North, Toronto, Canada, Sept. 12-14, 2005.

 “Mixed-Signal CMOS Haar Wavelet Compression Imager Architecture,” A. Olyaei, R. Genov, Midwest Symposium on Circuits and Systems (MWSCAS’05), Cincinnati, Ohio, Aug. 7-10, 2005.

“CMOS Wavelet Compression Imager Architecture,” A. Olyaei, R. Genov, IEEE CAS Emerging Technologies Workshop, St. Petersburg, Russia, , June 23-24, 2005 (invited).

“Minimal Activity Mixed-Signal VLSI Architecture for Real-Time Linear Transforms in Video,” R. Karakiewicz and R. Genov, IEEE Int. Symp. on Circuits and Systems (ISCAS'2005), Kobe, Japan, May 23-26, 2005.

“A 1GMACS/mW Mixed-Signal Differential-Charge CID/DRAM Processor,” R. Genov, IEEE Int. Conf.  on Circuits and Systems for Communications (ICCSC’2004), Moscow, Russia, June 30 - July 2, 2004 (invited).  

“Integrated Multi-Electrode Fluidic Nitric-Oxide Sensor and VLSI Potentiostat Array,” M. Naware, A. Rege, R. Genov, M. Stanacevic, G. Cauwenberghs, N. Thakor, IEEE Int. Symp. on Circuits and Systems (ISCAS'2004), Vancouver, Canada, May 26-29, 2004.

“VLSI Multi-Channel Track-and-Hold Potentiostat,” R. Genov, M. Stanacevic, M. Naware, G. Cauwenberghs, N. Thakor, in Microtechnologies for the New Millennium, Bioengineered and Bioinspired Systems 2003, Proc. SPIE vol. 5119, May 2003.

“Algorithmic Partial Analog-to-Digital Conversion in Mixed-Signal Array Processors,” R. Genov, G. Cauwenberghs, Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS'2003), Bangkok, Thailand, May 25-28, 2003.

 “A 5.9mW 6.5GMACS CID/DRAM Array Processor,” R. Genov, G. Cauwenberghs, G. Mulliken, and F. Adil, Proc. European Solid-State Circuits Conference (ESSCIRC’2002), Florence, Italy, Sept. 24-26, 2002.

“Kerneltron: Support Vector ‘Machine’ in Silicon,” R. Genov, G. Cauwenberghs, Proc. SVM’2002, Lecture Notes in Computer Science, Niagara Falls, ON, Aug. 10, 2002.

“Delta-Sigma Algorithmic Analog-to-Digital Conversion,” G. Mulliken, F. Adil, G. Cauwenberghs, and  R. Genov, Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS'2002), Phoenix, AZ, May 26-29, 2002.

“Charge-Based MOS Correlated Double Sampling Comparator and Folding Circuit,” R. Genov and G. Cauwenberghs, Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS'2002), Phoenix, AZ, May 26-29, 2002.

“Neuromorphic Processor for Real-Time Biosonar Object Detection ,” G. Cauwenberghs, R. T. Edwards, Y. Deng, R. Genov, and D. Lemonds, Proc. IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP’2002), Orlando, FL, May 13-17, 2002.

“Stochastic Mixed-Signal VLSI Architecture for High-Dimensional Kernel Machines,” R. Genov, G. Cauwenberghs, Advances in Neural Information Processing Systems (NIPS'2001), Cambridge, MA: MIT Press, vol. 14, 2002.

“CID/DRAM Mixed-Signal Parallel Distributed Array Processor,” R. Genov, G. Cauwenberghs, 14th International IEEE ASIC/SOC Conference (ASIC/SOC'2001), Washington, DC, Sept. 12-15, 2001.

“Embedded Dynamic Memory and Charge-Mode Logic for Parallel Array Processing,” R. Genov, G. Cauwenberghs, Proc. of the 5th World Multi-Conference on Systemics, Cybernetics and Informatics (SCI'2001), Orlando, FL, July 22-25, 2001.

“Massively Parallel Inner-Product Array Processor,” R. Genov, G. Cauwenberghs, Proc. of Int. Joint Conference on Neural Networks (IJCNN'2001), Washington, DC, July 15-19, 2001.

“Analog Array Processor with Digital Resolution Enhancement and Offset Compensation,” R. Genov, G. Cauwenberghs, Proc. of Conference on Information Sciences and Systems (CISS'2001), Baltimore, MD, March 21-23, 2001.

“Charge-Mode Parallel Architecture for Matrix-Vector Multiplication,” R. Genov and G. Cauwenberghs, Proc. of 43rd IEEE Midwest Symposium on Circuits and Systems (MWSCAS'2000), Lansing, MI, Aug. 8-11, 2000. (Best Student Paper Award, 3rd place.)

“Learning to Navigate from Limited Sensory Input: Experiments with the Khepera Microrobot,” R. Genov, S. Madhavapeddi and G. Cauwenberghs, Proc. of International Joint Conference on Neural Networks (IJCNN'99), Washington, DC, vol. 3, pp. 2061-2064, 1999. (Best Presentation Award.)

“16-Channel Single-Chip Current-Mode Track-and-Hold Acquisition System with 100 dB Dynamic Range,” R. Genov and G. Cauwenberghs, Proc. of IEEE International Symposium on Circuits and Systems (ISCAS'99), Orlando, FL, vol. 6, pp. 350-353, 1999. (Best Student Paper Contest Finalist.)

PATENTS

“High-Precision Matrix-Vector Multiplication on a Charge-Mode Array with Embedded Dynamic Memory and Stochastic Method Thereof,” R. Genov and G. Cauwenberghs, US patent pending, filing date Dec. 4, 2003.