################################################## ## ## ## C A L I B R E S Y S T E M ## ## ## ## L V S R E P O R T ## ## ## ################################################## REPORT FILE NAME: CHIP.lvs.report LAYOUT NAME: CHIP.sp ('CHIP') SOURCE NAME: CHIP.src.net ('CHIP') RULE FILE: /ali/r/r2/mcleod/CMOS90NM/lvsRunDir/_calibrelvs_cgi_ RULE FILE TITLE: CALIBRE cmos090 LVS RULES FILE, Common technology kit team - Crolles2, dated Date: Thu Feb 10 17:28:05 2005 $ HCELL FILE: (-automatch) CREATION TIME: Sun Dec 17 13:23:56 2006 CURRENT DIRECTORY: /ali/r/r2/mcleod/CMOS90NM/lvsRunDir USER NAME: mcleod CALIBRE VERSION: v2005.3_6.10 Mon Aug 29 12:59:28 PDT 2005 OVERALL COMPARISON RESULTS # ################### _ _ # # # * * # # # CORRECT # | # # # # \___/ # ################### ************************************************************************************************************** CELL SUMMARY ************************************************************************************************************** Result Layout Source ----------- ----------- -------------- CORRECT INV3 INV3 CORRECT INV4 INV4 CORRECT COMP2 COMP2 CORRECT CP2 CP2 CORRECT Latch Latch CORRECT PI2 PI2 CORRECT PI_CTRL PI_CTRL CORRECT REFGEN REFGEN CORRECT VI3 VI3 CORRECT PI_CLKBUF PI_CLKBUF CORRECT XOR XOR CORRECT PD PD CORRECT CDR CDR CORRECT CHIP CHIP ************************************************************************************************************** LVS PARAMETERS ************************************************************************************************************** o LVS Setup: // LVS COMPONENT TYPE PROPERTY // LVS COMPONENT SUBTYPE PROPERTY // LVS PIN NAME PROPERTY LVS POWER NAME "VDD" "vdd" "vdd!" "vdd;" "VDDS" "vdds" "vdds!" "vdds;" LVS GROUND NAME "GND" "gnd" "gnd!" "gnd;" "GNDS" "gnds" "gnds!" "gnds;" LVS RECOGNIZE GATES NONE LVS IGNORE PORTS NO LVS CHECK PORT NAMES YES LVS BUILTIN DEVICE PIN SWAP YES LVS ALL CAPACITOR PINS SWAPPABLE NO LVS DISCARD PINS BY DEVICE NO LVS SOFT SUBSTRATE PINS NO LVS INJECT LOGIC NO LVS EXPAND UNBALANCED CELLS YES LVS EXPAND SEED PROMOTIONS NO LVS PRESERVE PARAMETERIZED CELLS NO LVS GLOBALS ARE PORTS YES LVS REVERSE WL NO LVS SPICE PREFER PINS NO LVS SPICE SLASH IS SPACE YES LVS SPICE ALLOW FLOATING PINS YES LVS SPICE ALLOW UNQUOTED STRINGS NO LVS SPICE CONDITIONAL LDD NO LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO LVS SPICE IMPLIED MOS AREA NO // LVS SPICE MULTIPLIER NAME LVS SPICE OVERRIDE GLOBALS NO LVS SPICE REDEFINE PARAM NO LVS SPICE REPLICATE DEVICES YES LVS SPICE STRICT WL NO // LVS SPICE OPTION LVS STRICT SUBTYPES NO LAYOUT CASE YES SOURCE CASE YES LVS COMPARE CASE NAMES TYPES LVS DOWNCASE DEVICE NO LVS REPORT MAXIMUM 50 LVS PROPERTY RESOLUTION MAXIMUM ALL // LVS SIGNATURE MAXIMUM LVS FILTER UNUSED OPTION AB O RC RG LVS REPORT OPTION A B C D LVS REPORT UNITS YES // LVS NON USER NAME PORT // LVS NON USER NAME NET // LVS NON USER NAME INSTANCE // Reduction LVS REDUCE SERIES MOS NO LVS REDUCE PARALLEL MOS YES LVS REDUCE SEMI SERIES MOS NO LVS REDUCE SPLIT GATES YES LVS REDUCE PARALLEL BIPOLAR YES LVS REDUCE SERIES CAPACITORS NO LVS REDUCE PARALLEL CAPACITORS YES LVS REDUCE SERIES RESISTORS YES LVS REDUCE PARALLEL RESISTORS YES LVS REDUCE PARALLEL DIODES YES LVS REDUCE D(DGNSVT25) PARALLEL [ TOLERANCE L 0 W 0 ] LVS REDUCE D(DGPSVT25) PARALLEL [ TOLERANCE L 0 W 0 ] LVS REDUCE D(DGNSVT33) PARALLEL [ TOLERANCE L 0 W 0 ] LVS REDUCE D(DGPSVT33) PARALLEL [ TOLERANCE L 0 W 0 ] LVS REDUCE MN(NLVT) PARALLEL [ TOLERANCE L 0 ] LVS REDUCE MN(NSVT) PARALLEL [ TOLERANCE L 0 ] LVS REDUCE MN(NSVTRPO) PARALLEL [ TOLERANCE L 0 ] LVS REDUCE MN(NSVT25) PARALLEL [ TOLERANCE L 0 ] LVS REDUCE MN(NSVT25RPO) PARALLEL [ TOLERANCE L 0 ] LVS REDUCE MN(NSVT25RPONOLDD) PARALLEL [ TOLERANCE L 0 ] LVS REDUCE MN(NSVT33) PARALLEL [ TOLERANCE L 0 ] LVS REDUCE MN(NSVT33RPO) PARALLEL [ TOLERANCE L 0 ] LVS REDUCE MN(NSVT33RPONOLDD) PARALLEL [ TOLERANCE L 0 ] LVS REDUCE MN(NHVT) PARALLEL [ TOLERANCE L 0 ] LVS REDUCE MN(NHVTRPO) PARALLEL [ TOLERANCE L 0 ] LVS REDUCE MN(NHVTPGDP) PARALLEL [ TOLERANCE L 0 ] LVS REDUCE MN(NSVTPGDP) PARALLEL [ TOLERANCE L 0 ] LVS REDUCE MN(NHVTPDDP) PARALLEL [ TOLERANCE L 0 ] LVS REDUCE MN(NSVTPDDP) PARALLEL [ TOLERANCE L 0 ] LVS REDUCE MN(NHVTPGSP) PARALLEL [ TOLERANCE L 0 ] LVS REDUCE MN(NSVTPGSP) PARALLEL [ TOLERANCE L 0 ] LVS REDUCE MN(NHVTPDSP) PARALLEL [ TOLERANCE L 0 ] LVS REDUCE MN(NSVTPDSP) PARALLEL [ TOLERANCE L 0 ] LVS REDUCE MP(PLVT) PARALLEL [ TOLERANCE L 0 ] LVS REDUCE MP(PSVT) PARALLEL [ TOLERANCE L 0 ] LVS REDUCE MP(PSVTRPO) PARALLEL [ TOLERANCE L 0 ] LVS REDUCE MP(PSVT25) PARALLEL [ TOLERANCE L 0 ] LVS REDUCE MP(PSVT25RPO) PARALLEL [ TOLERANCE L 0 ] LVS REDUCE MP(PSVT33) PARALLEL [ TOLERANCE L 0 ] LVS REDUCE MP(PSVT33RPO) PARALLEL [ TOLERANCE L 0 ] LVS REDUCE MP(PHVT) PARALLEL [ TOLERANCE L 0 ] LVS REDUCE MP(PHVTRPO) PARALLEL [ TOLERANCE L 0 ] LVS REDUCE MP(PHVTPUSP) PARALLEL [ TOLERANCE L 0 ] LVS REDUCE MP(PSVTPUSP) PARALLEL [ TOLERANCE L 0 ] LVS REDUCE MP(PHVTPUDP) PARALLEL [ TOLERANCE L 0 ] LVS REDUCE MP(PSVTPUDP) PARALLEL [ TOLERANCE L 0 ] LVS REDUCE LDDN(ndr25) PARALLEL [ TOLERANCE L 0 SIDENUM 0 ] LVS REDUCE pdr25 PARALLEL [ TOLERANCE L 0 SIDENUM 0 ] LVS REDUCE R(RHIPORPO) PARALLEL [ TOLERANCE L 0 W 0 ] LVS REDUCE R(RHIPORPO) SERIES POS NEG [ TOLERANCE W 0 ] LVS REDUCE R(RNPORPO) PARALLEL [ TOLERANCE L 0 W 0 ] LVS REDUCE R(RNPORPO) SERIES POS NEG [ TOLERANCE W 0 ] LVS REDUCE R(RNWOD) PARALLEL [ TOLERANCE L 0 W 0 ] LVS REDUCE R(RNWOD) SERIES POS NEG [ TOLERANCE W 0 ] LVS REDUCE R(RPODRPO) PARALLEL [ TOLERANCE L 0 W 0 ] LVS REDUCE R(RPODRPO) SERIES POS NEG [ TOLERANCE W 0 ] LVS REDUCE R(RNODRPO) PARALLEL [ TOLERANCE L 0 W 0 ] LVS REDUCE R(RNODRPO) SERIES POS NEG [ TOLERANCE W 0 ] LVS REDUCE R(RPPORPO) PARALLEL [ TOLERANCE L 0 W 0 ] LVS REDUCE R(RPPORPO) SERIES POS NEG [ TOLERANCE W 0 ] LVS REDUCE R(RNPO) PARALLEL [ TOLERANCE L 0 W 0 ] LVS REDUCE R(RNPO) SERIES POS NEG [ TOLERANCE W 0 ] LVS REDUCE R(RM1) PARALLEL [ TOLERANCE L 0 W 0 ] LVS REDUCE R(RM1) SERIES POS NEG [ TOLERANCE W 0 ] LVS REDUCE R(RM2) PARALLEL [ TOLERANCE L 0 W 0 ] LVS REDUCE R(RM2) SERIES POS NEG [ TOLERANCE W 0 ] LVS REDUCE R(RM3) PARALLEL [ TOLERANCE L 0 W 0 ] LVS REDUCE R(RM3) SERIES POS NEG [ TOLERANCE W 0 ] LVS REDUCE R(RM4) PARALLEL [ TOLERANCE L 0 W 0 ] LVS REDUCE R(RM4) SERIES POS NEG [ TOLERANCE W 0 ] LVS REDUCE R(RM5) PARALLEL [ TOLERANCE L 0 W 0 ] LVS REDUCE R(RM5) SERIES POS NEG [ TOLERANCE W 0 ] LVS REDUCE R(RM6) PARALLEL [ TOLERANCE L 0 W 0 ] LVS REDUCE R(RM6) SERIES POS NEG [ TOLERANCE W 0 ] LVS REDUCE R(RNPOI) PARALLEL [ TOLERANCE L 0 W 0 ] LVS REDUCE R(RNPOI) SERIES POS NEG [ TOLERANCE W 0 ] LVS REDUCE R(RPPOI) PARALLEL [ TOLERANCE L 0 W 0 ] LVS REDUCE R(RPPOI) SERIES POS NEG [ TOLERANCE W 0 ] LVS REDUCE R(RAP) PARALLEL [ TOLERANCE L 0 W 0 ] LVS REDUCE R(RAP) SERIES POS NEG [ TOLERANCE W 0 ] LVS REDUCE C(CPONW) PARALLEL LVS REDUCE C(CPOPW) PARALLEL LVS REDUCE C(CPO25NW) PARALLEL LVS REDUCE C(CPO33NW) PARALLEL LVS REDUCE C(CPO25PW) PARALLEL LVS REDUCE C(CPO33PW) PARALLEL LVS REDUCE C(CMIMMK) PARALLEL LVS REDUCE C(CE1E2) PARALLEL LVS REDUCE C(CM1M2) PARALLEL LVS REDUCE C(CM2M3) PARALLEL LVS REDUCE C(CM3M4) PARALLEL LVS REDUCE C(CM4M5) PARALLEL LVS REDUCE C(CM5M6) PARALLEL LVS REDUCE C(CM6M7) PARALLEL LVS REDUCE C(CM7M8) PARALLEL LVS REDUCE C(CM8M9) PARALLEL LVS REDUCE C(CM1M2I) PARALLEL LVS REDUCE C(CM2M3I) PARALLEL LVS REDUCE C(CM3M4I) PARALLEL LVS REDUCE C(CM4M5I) PARALLEL LVS REDUCE C(CM5M6I) PARALLEL LVS REDUCE C(CM6M7I) PARALLEL LVS REDUCE C(CM7M8I) PARALLEL LVS REDUCE C(CM8M9I) PARALLEL LVS REDUCE C(CMSBE) PARALLEL [ TOLERANCE BOTLAYER 0 TOPLAYER 0 ] LVS REDUCE Q(NPNISO4) PARALLEL [ TOLERANCE AE 0 PE 0 ] LVS REDUCE Q(NPNISO25) PARALLEL [ TOLERANCE AE 0 PE 0 ] LVS REDUCE Q(PNPS4) PARALLEL [ TOLERANCE AE 0 PE 0 ] LVS REDUCE Q(PNPS25) PARALLEL [ TOLERANCE AE 0 PE 0 ] LVS REDUCE C(CFRM1) SERIES POS NEG NO LVS REDUCE C(CFRM1) PARALLEL [ TOLERANCE FS 0 L 0 ] LVS REDUCE C(CFRM2) SERIES POS NEG NO LVS REDUCE C(CFRM2) PARALLEL [ TOLERANCE FS 0 L 0 ] LVS REDUCE C(CFRM3) SERIES POS NEG NO LVS REDUCE C(CFRM3) PARALLEL [ TOLERANCE FS 0 L 0 ] LVS REDUCE C(CFRM4) SERIES POS NEG NO LVS REDUCE C(CFRM4) PARALLEL [ TOLERANCE FS 0 L 0 ] LVS REDUCE C(CFRM5) SERIES POS NEG NO LVS REDUCE C(CFRM5) PARALLEL [ TOLERANCE FS 0 L 0 ] LVS REDUCE C(CFRM6) SERIES POS NEG NO LVS REDUCE C(CFRM6) PARALLEL [ TOLERANCE FS 0 L 0 ] LVS REDUCE C(CFRM7) SERIES POS NEG NO LVS REDUCE C(CFRM7) PARALLEL [ TOLERANCE FS 0 L 0 ] LVS REDUCE C(CFRM8) SERIES POS NEG NO LVS REDUCE C(CFRM8) PARALLEL [ TOLERANCE FS 0 L 0 ] LVS REDUCE C(CFRM9) SERIES POS NEG NO LVS REDUCE C(CFRM9) PARALLEL [ TOLERANCE FS 0 L 0 ] // Trace Property TRACE PROPERTY mn(nsvtrpo) w w 1 TRACE PROPERTY mn(nsvtrpo) l l 0 TRACE PROPERTY mp(psvtrpo) w w 1 TRACE PROPERTY mp(psvtrpo) l l 0 TRACE PROPERTY mn(nsvt) w w 1 TRACE PROPERTY mn(nsvt) l l 0 TRACE PROPERTY mp(psvt) w w 1 TRACE PROPERTY mp(psvt) l l 0 TRACE PROPERTY mn(nhvt) w w 1 TRACE PROPERTY mn(nhvt) l l 0 TRACE PROPERTY mp(phvt) w w 1 TRACE PROPERTY mp(phvt) l l 0 TRACE PROPERTY mn(nlvt) w w 1 TRACE PROPERTY mn(nlvt) l l 0 TRACE PROPERTY mp(plvt) w w 1 TRACE PROPERTY mp(plvt) l l 0 TRACE PROPERTY mn(nhvtrpo) w w 1 TRACE PROPERTY mn(nhvtrpo) l l 0 TRACE PROPERTY mp(phvtrpo) w w 1 TRACE PROPERTY mp(phvtrpo) l l 0 TRACE PROPERTY mn(nhvtpgdp) w w 1 TRACE PROPERTY mn(nhvtpgdp) l l 0 TRACE PROPERTY mn(nsvtpgdp) w w 1 TRACE PROPERTY mn(nsvtpgdp) l l 0 TRACE PROPERTY mn(nhvtpddp) w w 1 TRACE PROPERTY mn(nhvtpddp) l l 0 TRACE PROPERTY mn(nsvtpddp) w w 1 TRACE PROPERTY mn(nsvtpddp) l l 0 TRACE PROPERTY mn(nhvtpgsp) w w 1 TRACE PROPERTY mn(nhvtpgsp) l l 0 TRACE PROPERTY mn(nsvtpgsp) w w 1 TRACE PROPERTY mn(nsvtpgsp) l l 0 TRACE PROPERTY mn(nhvtpdsp) w w 1 TRACE PROPERTY mn(nhvtpdsp) l l 0 TRACE PROPERTY mn(nsvtpdsp) w w 1 TRACE PROPERTY mn(nsvtpdsp) l l 0 TRACE PROPERTY mp(phvtpusp) w w 1 TRACE PROPERTY mp(phvtpusp) l l 0 TRACE PROPERTY mp(psvtpusp) w w 1 TRACE PROPERTY mp(psvtpusp) l l 0 TRACE PROPERTY mp(phvtpudp) w w 1 TRACE PROPERTY mp(phvtpudp) l l 0 TRACE PROPERTY mp(psvtpudp) w w 1 TRACE PROPERTY mp(psvtpudp) l l 0 TRACE PROPERTY mn(nsvt33) w w 1 TRACE PROPERTY mn(nsvt33) l l 0 TRACE PROPERTY mn(nsvt33rpo) w w 1 TRACE PROPERTY mn(nsvt33rpo) l l 0 TRACE PROPERTY mn(nsvt33rponoldd) w w 1 TRACE PROPERTY mn(nsvt33rponoldd) l l 0 TRACE PROPERTY mp(psvt33) w w 1 TRACE PROPERTY mp(psvt33) l l 0 TRACE PROPERTY mp(psvt33rpo) w w 1 TRACE PROPERTY mp(psvt33rpo) l l 0 TRACE PROPERTY mn(nsvt25) w w 1 TRACE PROPERTY mn(nsvt25) l l 0 TRACE PROPERTY mn(nsvt25rpo) w w 1 TRACE PROPERTY mn(nsvt25rpo) l l 0 TRACE PROPERTY mn(nsvt25rponoldd) w w 1 TRACE PROPERTY mn(nsvt25rponoldd) l l 0 TRACE PROPERTY mp(psvt25) w w 1 TRACE PROPERTY mp(psvt25) l l 0 TRACE PROPERTY mp(psvt25rpo) w w 1 TRACE PROPERTY mp(psvt25rpo) l l 0 TRACE PROPERTY lddn(ndr25) w w 1 TRACE PROPERTY lddn(ndr25) l l 0 TRACE PROPERTY lddn(ndr25) sidenum sidenum 0 TRACE PROPERTY pdr25 w w 1 TRACE PROPERTY pdr25 l l 0 TRACE PROPERTY pdr25 sidenum sidenum 0 TRACE PROPERTY d(dgnsvt25) w w 0 TRACE PROPERTY d(dgnsvt25) l l 0 TRACE PROPERTY d(dgnsvt25) nfing nfing 0 TRACE PROPERTY d(dgnsvt33) w w 0 TRACE PROPERTY d(dgnsvt33) l l 0 TRACE PROPERTY d(dgnsvt33) nfing nfing 0 TRACE PROPERTY d(dgpsvt25) w w 0 TRACE PROPERTY d(dgpsvt25) l l 0 TRACE PROPERTY d(dgpsvt25) nfing nfing 0 TRACE PROPERTY d(dgpsvt33) w w 0 TRACE PROPERTY d(dgpsvt33) l l 0 TRACE PROPERTY d(dgpsvt33) nfing nfing 0 TRACE PROPERTY ebeamprobe(ebeamprobe) area area 1 TRACE PROPERTY ebeamprobe(ebeamprobe) peri peri 1 TRACE PROPERTY microprobe(microprobe) area area 1 TRACE PROPERTY microprobe(microprobe) peri peri 1 TRACE PROPERTY d(dnsvt) a a 1 TRACE PROPERTY d(dnsvt) p p 1 TRACE PROPERTY d(dnhvt) a a 1 TRACE PROPERTY d(dnhvt) p p 1 TRACE PROPERTY d(dnlvt) a a 1 TRACE PROPERTY d(dnlvt) p p 1 TRACE PROPERTY d(dpsvt) a a 1 TRACE PROPERTY d(dpsvt) p p 1 TRACE PROPERTY d(dphvt) a a 1 TRACE PROPERTY d(dphvt) p p 1 TRACE PROPERTY d(dplvt) a a 1 TRACE PROPERTY d(dplvt) p p 1 TRACE PROPERTY d(dnsvt33) a a 1 TRACE PROPERTY d(dnsvt33) p p 1 TRACE PROPERTY d(dnsvt25) a a 1 TRACE PROPERTY d(dnsvt25) p p 1 TRACE PROPERTY d(dpsvt33) a a 1 TRACE PROPERTY d(dpsvt33) p p 1 TRACE PROPERTY d(dpsvt25) a a 1 TRACE PROPERTY d(dpsvt25) p p 1 TRACE PROPERTY r(rnpoi) w w 0 TRACE PROPERTY r(rnpoi) l l 0 TRACE PROPERTY r(rppoi) w w 0 TRACE PROPERTY r(rppoi) l l 0 TRACE PROPERTY r(rm1) w w 0 TRACE PROPERTY r(rm1) l l 0 TRACE PROPERTY r(rm2) w w 0 TRACE PROPERTY r(rm2) l l 0 TRACE PROPERTY r(rm3) w w 0 TRACE PROPERTY r(rm3) l l 0 TRACE PROPERTY r(rm4) w w 0 TRACE PROPERTY r(rm4) l l 0 TRACE PROPERTY r(rm5) w w 0 TRACE PROPERTY r(rm5) l l 0 TRACE PROPERTY r(rm6) w w 0 TRACE PROPERTY r(rm6) l l 0 TRACE PROPERTY r(rm7) w w 0 TRACE PROPERTY r(rm7) l l 0 TRACE PROPERTY r(rap) w w 0 TRACE PROPERTY r(rap) l l 0 TRACE PROPERTY r(rhiporpo) w w 0 TRACE PROPERTY r(rhiporpo) l l 0 TRACE PROPERTY r(rnodrpo) w w 0 TRACE PROPERTY r(rnodrpo) l l 0 TRACE PROPERTY r(rnwod) w w 0 TRACE PROPERTY r(rnwod) l l 0 TRACE PROPERTY r(rpodrpo) w w 0 TRACE PROPERTY r(rpodrpo) l l 0 TRACE PROPERTY r(rnporpo) w w 0 TRACE PROPERTY r(rnporpo) l l 0 TRACE PROPERTY r(rpporpo) w w 0 TRACE PROPERTY r(rpporpo) l l 0 TRACE PROPERTY r(rnpo) w w 0 TRACE PROPERTY r(rnpo) l l 0 TRACE PROPERTY c(cpo33nw) carea carea 0 TRACE PROPERTY c(cpo33nw) cperi cperi 0 TRACE PROPERTY c(cpo25nw) carea carea 0 TRACE PROPERTY c(cpo25nw) cperi cperi 0 TRACE PROPERTY cfrm1m5(cfrm1m5) nf nf 0 TRACE PROPERTY cfrm1m5(cfrm1m5) l l 0 TRACE PROPERTY c(cmimmk) carea carea 0 TRACE PROPERTY c(cmimmk) cperi cperi 0 TRACE PROPERTY c(cm1m2) carea carea 0 TRACE PROPERTY c(cm1m2) cperi cperi 0 TRACE PROPERTY c(cm1m2i) carea carea 0 TRACE PROPERTY c(cm1m2i) cperi cperi 0 TRACE PROPERTY c(cm2m3) carea carea 0 TRACE PROPERTY c(cm2m3) cperi cperi 0 TRACE PROPERTY c(cm2m3i) carea carea 0 TRACE PROPERTY c(cm2m3i) cperi cperi 0 TRACE PROPERTY c(cm3m4) carea carea 0 TRACE PROPERTY c(cm3m4) cperi cperi 0 TRACE PROPERTY c(cm3m4i) carea carea 0 TRACE PROPERTY c(cm3m4i) cperi cperi 0 TRACE PROPERTY c(cm4m5) carea carea 0 TRACE PROPERTY c(cm4m5) cperi cperi 0 TRACE PROPERTY c(cm4m5i) carea carea 0 TRACE PROPERTY c(cm4m5i) cperi cperi 0 TRACE PROPERTY c(cm5m6) carea carea 0 TRACE PROPERTY c(cm5m6) cperi cperi 0 TRACE PROPERTY c(cm5m6i) carea carea 0 TRACE PROPERTY c(cm5m6i) cperi cperi 0 TRACE PROPERTY c(cm6m7) carea carea 0 TRACE PROPERTY c(cm6m7) cperi cperi 0 TRACE PROPERTY c(cm6m7i) carea carea 0 TRACE PROPERTY c(cm6m7i) cperi cperi 0 TRACE PROPERTY c(cm7m8) carea carea 0 TRACE PROPERTY c(cm7m8) cperi cperi 0 TRACE PROPERTY c(cm7m8i) carea carea 0 TRACE PROPERTY c(cm7m8i) cperi cperi 0 TRACE PROPERTY c(cm8m9) carea carea 0 TRACE PROPERTY c(cm8m9) cperi cperi 0 TRACE PROPERTY c(cm8m9i) carea carea 0 TRACE PROPERTY c(cm8m9i) cperi cperi 0 TRACE PROPERTY c(cfrm1) l l 0 TRACE PROPERTY c(cfrm1) fs fs 0 TRACE PROPERTY c(cfrm2) l l 0 TRACE PROPERTY c(cfrm2) fs fs 0 TRACE PROPERTY c(cfrm3) l l 0 TRACE PROPERTY c(cfrm3) fs fs 0 TRACE PROPERTY c(cfrm4) l l 0 TRACE PROPERTY c(cfrm4) fs fs 0 TRACE PROPERTY c(cfrm5) l l 0 TRACE PROPERTY c(cfrm5) fs fs 0 TRACE PROPERTY c(cfrm6) l l 0 TRACE PROPERTY c(cfrm6) fs fs 0 TRACE PROPERTY c(cfrm7) l l 0 TRACE PROPERTY c(cfrm7) fs fs 0 TRACE PROPERTY c(cfrm8) l l 0 TRACE PROPERTY c(cfrm8) fs fs 0 TRACE PROPERTY c(cfrm9) l l 0 TRACE PROPERTY c(cfrm9) fs fs 0 TRACE PROPERTY c(cmsbe) carea carea 0 TRACE PROPERTY c(cmsbe) cperi cperi 0 TRACE PROPERTY c(cmsbe) botlayer botlayer 0 TRACE PROPERTY c(cmsbe) toplayer toplayer 0 TRACE PROPERTY mn(nsvt33dram) w w 1 TRACE PROPERTY mn(nsvt33dram) l l 0 TRACE PROPERTY mn(nsvt25dram) w w 1 TRACE PROPERTY mn(nsvt25dram) l l 0 TRACE PROPERTY c(ce1e2) carea carea 0 TRACE PROPERTY c(ce1e2) cperi cperi 0 TRACE PROPERTY lddn(nsvt25drift) w w 1 TRACE PROPERTY lddn(nsvt25drift) l l 0 TRACE PROPERTY c(cponw) carea carea 0 TRACE PROPERTY c(cponw) cperi cperi 0 TRACE PROPERTY c(cpopw) carea carea 0 TRACE PROPERTY c(cpopw) cperi cperi 0 TRACE PROPERTY c(cpo33pw) carea carea 0 TRACE PROPERTY c(cpo33pw) cperi cperi 0 TRACE PROPERTY c(cpo25pw) carea carea 0 TRACE PROPERTY c(cpo25pw) cperi cperi 0 TRACE PROPERTY ldd(mtpcell) l l 1 TRACE PROPERTY ldd(mtpcell) w w 1 TRACE PROPERTY mp(psvt25_mtp) l l 1 TRACE PROPERTY mp(psvt25_mtp) w w 1 TRACE PROPERTY mp(psvt25rpo_mtp) l l 1 TRACE PROPERTY mp(psvt25rpo_mtp) w w 1 CELL COMPARISON RESULTS # ################### _ _ # # # * * # # # CORRECT # | # # # # \___/ # ################### LAYOUT CELL NAME: INV3 SOURCE CELL NAME: INV3 -------------------------------------------------------------------------------------------------------------- INITIAL NUMBERS OF OBJECTS -------------------------- Layout Source Component Type ------ ------ -------------- Ports: 4 4 Nets: 4 4 Instances: 1 1 MN (4 pins) 3 3 MP (4 pins) ------ ------ Total Inst: 4 4 NUMBERS OF OBJECTS AFTER TRANSFORMATION --------------------------------------- Layout Source Component Type ------ ------ -------------- Ports: 4 4 Nets: 4 4 Instances: 1 1 MN (4 pins) 1 1 MP (4 pins) ------ ------ Total Inst: 2 2 ************************************************************************************************************** INFORMATION AND WARNINGS ************************************************************************************************************** Matched Matched Unmatched Unmatched Component Layout Source Layout Source Type ------- ------- --------- --------- --------- Ports: 4 4 0 0 Nets: 4 4 0 0 Instances: 1 1 0 0 MN(nsvt) 1 1 0 0 MP(psvt) ------- ------- --------- --------- Total Inst: 2 2 0 0 o Statistics: 3 layout mos transistors were reduced to 1. 2 mos transistors were deleted by parallel reduction. 3 source mos transistors were reduced to 1. 2 mos transistors were deleted by parallel reduction. o Initial Correspondence Points: Ports: VDD vin vout VSS CELL COMPARISON RESULTS # ################### _ _ # # # * * # # # CORRECT # | # # # # \___/ # ################### LAYOUT CELL NAME: INV4 SOURCE CELL NAME: INV4 -------------------------------------------------------------------------------------------------------------- INITIAL NUMBERS OF OBJECTS -------------------------- Layout Source Component Type ------ ------ -------------- Ports: 4 4 Nets: 4 4 Instances: 4 4 MN (4 pins) 12 12 MP (4 pins) ------ ------ Total Inst: 16 16 NUMBERS OF OBJECTS AFTER TRANSFORMATION --------------------------------------- Layout Source Component Type ------ ------ -------------- Ports: 4 4 Nets: 4 4 Instances: 1 1 MN (4 pins) 1 1 MP (4 pins) ------ ------ Total Inst: 2 2 ************************************************************************************************************** INFORMATION AND WARNINGS ************************************************************************************************************** Matched Matched Unmatched Unmatched Component Layout Source Layout Source Type ------- ------- --------- --------- --------- Ports: 4 4 0 0 Nets: 4 4 0 0 Instances: 1 1 0 0 MN(nsvt) 1 1 0 0 MP(psvt) ------- ------- --------- --------- Total Inst: 2 2 0 0 o Statistics: 16 layout mos transistors were reduced to 2. 14 mos transistors were deleted by parallel reduction. 16 source mos transistors were reduced to 2. 14 mos transistors were deleted by parallel reduction. o Initial Correspondence Points: Ports: VDD vin vout VSS CELL COMPARISON RESULTS # ################### _ _ # # # * * # # # CORRECT # | # # # # \___/ # ################### LAYOUT CELL NAME: COMP2 SOURCE CELL NAME: COMP2 -------------------------------------------------------------------------------------------------------------- INITIAL NUMBERS OF OBJECTS -------------------------- Layout Source Component Type ------ ------ -------------- Ports: 8 8 Nets: 20 20 Instances: 22 22 MN (4 pins) 28 28 MP (4 pins) 2 2 INV3 (4 pins) 2 2 INV4 (4 pins) ------ ------ Total Inst: 54 54 NUMBERS OF OBJECTS AFTER TRANSFORMATION --------------------------------------- Layout Source Component Type ------ ------ -------------- Ports: 8 8 Nets: 20 20 Instances: 11 11 MN (4 pins) 9 9 MP (4 pins) 2 2 INV3 (4 pins) 2 2 INV4 (4 pins) ------ ------ Total Inst: 24 24 ************************************************************************************************************** INFORMATION AND WARNINGS ************************************************************************************************************** Matched Matched Unmatched Unmatched Component Layout Source Layout Source Type ------- ------- --------- --------- --------- Ports: 8 8 0 0 Nets: 20 20 0 0 Instances: 11 11 0 0 MN(nsvt) 9 9 0 0 MP(psvt) 2 2 0 0 INV3 2 2 0 0 INV4 ------- ------- --------- --------- Total Inst: 24 24 0 0 o Statistics: 48 layout mos transistors were reduced to 18. 30 mos transistors were deleted by parallel reduction. 48 source mos transistors were reduced to 18. 30 mos transistors were deleted by parallel reduction. o Initial Correspondence Points: Ports: VDD irefpn vinn vinp latch VSS voutp voutn CELL COMPARISON RESULTS # ################### _ _ # # # * * # # # CORRECT # | # # # # \___/ # ################### LAYOUT CELL NAME: CP2 SOURCE CELL NAME: CP2 -------------------------------------------------------------------------------------------------------------- INITIAL NUMBERS OF OBJECTS -------------------------- Layout Source Component Type ------ ------ -------------- Ports: 10 10 Nets: 18 18 Instances: 24 24 MN (4 pins) 14 14 MP (4 pins) 2 2 C (3 pins) 2 2 R (2 pins) ------ ------ Total Inst: 42 42 NUMBERS OF OBJECTS AFTER TRANSFORMATION --------------------------------------- Layout Source Component Type ------ ------ -------------- Ports: 10 10 Nets: 18 18 Instances: 12 12 MN (4 pins) 7 7 MP (4 pins) 2 2 C (3 pins) 2 2 R (2 pins) ------ ------ Total Inst: 23 23 ************************************************************************************************************** INFORMATION AND WARNINGS ************************************************************************************************************** Matched Matched Unmatched Unmatched Component Layout Source Layout Source Type ------- ------- --------- --------- --------- Ports: 10 10 0 0 Nets: 18 18 0 0 Instances: 12 12 0 0 MN(nsvt) 7 7 0 0 MP(psvt) 2 2 0 0 C(cmimmk) 2 2 0 0 R(rppoi) ------- ------- --------- --------- Total Inst: 23 23 0 0 o Statistics: 38 layout mos transistors were reduced to 19. 19 mos transistors were deleted by parallel reduction. 38 source mos transistors were reduced to 19. 19 mos transistors were deleted by parallel reduction. o Initial Correspondence Points: Ports: VDD irefpn upp vcmref upn voutp voutn dnp dnn VSS CELL COMPARISON RESULTS # ################### _ _ # # # * * # # # CORRECT # | # # # # \___/ # ################### LAYOUT CELL NAME: Latch SOURCE CELL NAME: Latch -------------------------------------------------------------------------------------------------------------- INITIAL NUMBERS OF OBJECTS -------------------------- Layout Source Component Type ------ ------ -------------- Ports: 8 8 Nets: 10 10 Instances: 10 10 MN (4 pins) 2 2 R (2 pins) ------ ------ Total Inst: 12 12 NUMBERS OF OBJECTS AFTER TRANSFORMATION --------------------------------------- Layout Source Component Type ------ ------ -------------- Ports: 8 8 Nets: 10 10 Instances: 6 6 MN (4 pins) 2 2 R (2 pins) ------ ------ Total Inst: 8 8 ************************************************************************************************************** INFORMATION AND WARNINGS ************************************************************************************************************** Matched Matched Unmatched Unmatched Component Layout Source Layout Source Type ------- ------- --------- --------- --------- Ports: 8 8 0 0 Nets: 10 10 0 0 Instances: 2 2 0 0 MN(nhvt) 4 4 0 0 MN(nlvt) 2 2 0 0 R(rppoi) ------- ------- --------- --------- Total Inst: 8 8 0 0 o Statistics: 8 layout mos transistors were reduced to 4. 4 mos transistors were deleted by parallel reduction. 8 source mos transistors were reduced to 4. 4 mos transistors were deleted by parallel reduction. o Initial Correspondence Points: Ports: VDD DP DN CLKP CLKN QP QN VSS CELL COMPARISON RESULTS # ################### _ _ # # # * * # # # CORRECT # | # # # # \___/ # ################### LAYOUT CELL NAME: PI2 SOURCE CELL NAME: PI2 -------------------------------------------------------------------------------------------------------------- INITIAL NUMBERS OF OBJECTS -------------------------- Layout Source Component Type ------ ------ -------------- Ports: 12 12 Nets: 20 20 Instances: 48 48 MN (4 pins) 32 32 MP (4 pins) 2 2 R (2 pins) ------ ------ Total Inst: 82 82 NUMBERS OF OBJECTS AFTER TRANSFORMATION --------------------------------------- Layout Source Component Type ------ ------ -------------- Ports: 12 12 Nets: 20 20 Instances: 16 16 MN (4 pins) 8 8 MP (4 pins) 2 2 R (2 pins) ------ ------ Total Inst: 26 26 ************************************************************************************************************** INFORMATION AND WARNINGS ************************************************************************************************************** Matched Matched Unmatched Unmatched Component Layout Source Layout Source Type ------- ------- --------- --------- --------- Ports: 12 12 0 0 Nets: 20 20 0 0 Instances: 16 16 0 0 MN(nsvt) 8 8 0 0 MP(psvt) 2 2 0 0 R(rppoi) ------- ------- --------- --------- Total Inst: 26 26 0 0 o Statistics: 80 layout mos transistors were reduced to 24. 56 mos transistors were deleted by parallel reduction. 80 source mos transistors were reduced to 24. 56 mos transistors were deleted by parallel reduction. o Initial Correspondence Points: Ports: VDD CLKP CLKN I4 I3 I2 I1 CLK0 CLK180 CLK90 CLK270 VSS CELL COMPARISON RESULTS # ################### _ _ # # # * * # # # CORRECT # | # # # # \___/ # ################### LAYOUT CELL NAME: PI_CTRL SOURCE CELL NAME: PI_CTRL -------------------------------------------------------------------------------------------------------------- INITIAL NUMBERS OF OBJECTS -------------------------- Layout Source Component Type ------ ------ -------------- Ports: 20 20 Nets: 29 29 Instances: 152 152 MN (4 pins) 26 26 MP (4 pins) 4 4 R (2 pins) ------ ------ Total Inst: 182 182 NUMBERS OF OBJECTS AFTER TRANSFORMATION --------------------------------------- Layout Source Component Type ------ ------ -------------- Ports: 20 20 Nets: 29 29 Instances: 30 30 MN (4 pins) 3 3 MP (4 pins) 4 4 R (2 pins) ------ ------ Total Inst: 37 37 ************************************************************************************************************** INFORMATION AND WARNINGS ************************************************************************************************************** Matched Matched Unmatched Unmatched Component Layout Source Layout Source Type ------- ------- --------- --------- --------- Ports: 20 20 0 0 Nets: 29 29 0 0 Instances: 30 30 0 0 MN(nsvt) 3 3 0 0 MP(psvt) 4 4 0 0 R(rppoi) ------- ------- --------- --------- Total Inst: 37 37 0 0 o Statistics: 178 layout mos transistors were reduced to 33. 145 mos transistors were deleted by parallel reduction. 178 source mos transistors were reduced to 33. 145 mos transistors were deleted by parallel reduction. o Initial Correspondence Points: Ports: VDD vb2p vb2n vb1n vb1p i1in i2in b1p b1n b2n b2p VSS i1out<1> i1out<0> i2out<1> i2out<0> i3out<1> i3out<0> i4out<1> i4out<0> CELL COMPARISON RESULTS # ################### _ _ # # # * * # # # CORRECT # | # # # # \___/ # ################### LAYOUT CELL NAME: REFGEN SOURCE CELL NAME: REFGEN -------------------------------------------------------------------------------------------------------------- INITIAL NUMBERS OF OBJECTS -------------------------- Layout Source Component Type ------ ------ -------------- Ports: 11 11 Nets: 11 11 Instances: 112 112 MP (4 pins) ------ ------ Total Inst: 112 112 NUMBERS OF OBJECTS AFTER TRANSFORMATION --------------------------------------- Layout Source Component Type ------ ------ -------------- Ports: 11 11 Nets: 11 11 Instances: 10 10 MP (4 pins) ------ ------ Total Inst: 10 10 ************************************************************************************************************** INFORMATION AND WARNINGS ************************************************************************************************************** Matched Matched Unmatched Unmatched Component Layout Source Layout Source Type ------- ------- --------- --------- --------- Ports: 11 11 0 0 Nets: 11 11 0 0 Instances: 10 10 0 0 MP(psvt) ------- ------- --------- --------- Total Inst: 10 10 0 0 o Statistics: 112 layout mos transistors were reduced to 10. 102 mos transistors were deleted by parallel reduction. 112 source mos transistors were reduced to 10. 102 mos transistors were deleted by parallel reduction. o Initial Correspondence Points: Ports: VDD iref25np200u iref01np200u irefpncp irefpncompp irefpncompn irefpnvi irefpnclkbuf1 irefpnclkbuf2 irefpnxor1 irefpnxor2 CELL COMPARISON RESULTS # ################### _ _ # # # * * # # # CORRECT # | # # # # \___/ # ################### LAYOUT CELL NAME: VI3 SOURCE CELL NAME: VI3 -------------------------------------------------------------------------------------------------------------- INITIAL NUMBERS OF OBJECTS -------------------------- Layout Source Component Type ------ ------ -------------- Ports: 7 7 Nets: 11 11 Instances: 14 14 MN (4 pins) 16 16 MP (4 pins) 1 1 R (2 pins) ------ ------ Total Inst: 31 31 NUMBERS OF OBJECTS AFTER TRANSFORMATION --------------------------------------- Layout Source Component Type ------ ------ -------------- Ports: 7 7 Nets: 11 11 Instances: 5 5 MN (4 pins) 4 4 MP (4 pins) 1 1 R (2 pins) ------ ------ Total Inst: 10 10 ************************************************************************************************************** INFORMATION AND WARNINGS ************************************************************************************************************** Matched Matched Unmatched Unmatched Component Layout Source Layout Source Type ------- ------- --------- --------- --------- Ports: 7 7 0 0 Nets: 11 11 0 0 Instances: 5 5 0 0 MN(nsvt) 4 4 0 0 MP(psvt) 1 1 0 0 R(rppoi) ------- ------- --------- --------- Total Inst: 10 10 0 0 o Statistics: 30 layout mos transistors were reduced to 9. 21 mos transistors were deleted by parallel reduction. 30 source mos transistors were reduced to 9. 21 mos transistors were deleted by parallel reduction. o Initial Correspondence Points: Ports: VDD irefpn vinp vinn ioutn ioutp VSS CELL COMPARISON RESULTS # ################### _ _ # # # * * # # # CORRECT # | # # # # \___/ # ################### LAYOUT CELL NAME: PI_CLKBUF SOURCE CELL NAME: PI_CLKBUF -------------------------------------------------------------------------------------------------------------- INITIAL NUMBERS OF OBJECTS -------------------------- Layout Source Component Type ------ ------ -------------- Ports: 13 13 Nets: 16 16 Instances: 12 12 MN (4 pins) 2 2 R (2 pins) 1 1 PI2 (12 pins) ------ ------ Total Inst: 15 15 NUMBERS OF OBJECTS AFTER TRANSFORMATION --------------------------------------- Layout Source Component Type ------ ------ -------------- Ports: 13 13 Nets: 16 16 Instances: 4 4 MN (4 pins) 2 2 R (2 pins) 1 1 PI2 (12 pins) ------ ------ Total Inst: 7 7 ************************************************************************************************************** INFORMATION AND WARNINGS ************************************************************************************************************** Matched Matched Unmatched Unmatched Component Layout Source Layout Source Type ------- ------- --------- --------- --------- Ports: 13 13 0 0 Nets: 16 16 0 0 Instances: 2 2 0 0 MN(nhvt) 2 2 0 0 MN(nlvt) 2 2 0 0 R(rppoi) 1 1 0 0 PI2 ------- ------- --------- --------- Total Inst: 7 7 0 0 o Statistics: 12 layout mos transistors were reduced to 4. 8 mos transistors were deleted by parallel reduction. 12 source mos transistors were reduced to 4. 8 mos transistors were deleted by parallel reduction. o Initial Correspondence Points: Ports: VDD irefpn clkbufp clkbufn VSS I4 I3 I2 I1 clk0 clk270 clk180 clk90 CELL COMPARISON RESULTS # ################### _ _ # # # * * # # # CORRECT # | # # # # \___/ # ################### LAYOUT CELL NAME: XOR SOURCE CELL NAME: XOR -------------------------------------------------------------------------------------------------------------- INITIAL NUMBERS OF OBJECTS -------------------------- Layout Source Component Type ------ ------ -------------- Ports: 9 9 Nets: 12 12 Instances: 40 40 MN (4 pins) 2 2 R (2 pins) ------ ------ Total Inst: 42 42 NUMBERS OF OBJECTS AFTER TRANSFORMATION --------------------------------------- Layout Source Component Type ------ ------ -------------- Ports: 9 9 Nets: 12 12 Instances: 8 8 MN (4 pins) 2 2 R (2 pins) ------ ------ Total Inst: 10 10 ************************************************************************************************************** INFORMATION AND WARNINGS ************************************************************************************************************** Matched Matched Unmatched Unmatched Component Layout Source Layout Source Type ------- ------- --------- --------- --------- Ports: 9 9 0 0 Nets: 12 12 0 0 Instances: 2 2 0 0 MN(nlvt) 6 6 0 0 MN(nsvt) 2 2 0 0 R(rppoi) ------- ------- --------- --------- Total Inst: 10 10 0 0 o Statistics: 40 layout mos transistors were reduced to 8. 32 mos transistors were deleted by parallel reduction. 40 source mos transistors were reduced to 8. 32 mos transistors were deleted by parallel reduction. o Initial Correspondence Points: Ports: VDD OUTP OUTN irefpn BP BN AP AN VSS CELL COMPARISON RESULTS # ################### _ _ # # # * * # # # CORRECT # | # # # # \___/ # ################### LAYOUT CELL NAME: PD SOURCE CELL NAME: PD -------------------------------------------------------------------------------------------------------------- NUMBERS OF OBJECTS ------------------ Layout Source Component Type ------ ------ -------------- Ports: 18 18 Nets: 30 30 Instances: 8 8 Latch (8 pins) 2 2 XOR (9 pins) ------ ------ Total Inst: 10 10 ************************************************************************************************************** INFORMATION AND WARNINGS ************************************************************************************************************** Matched Matched Unmatched Unmatched Component Layout Source Layout Source Type ------- ------- --------- --------- --------- Ports: 18 18 0 0 Nets: 30 30 0 0 Instances: 8 8 0 0 Latch 2 2 0 0 XOR ------- ------- --------- --------- Total Inst: 10 10 0 0 o Initial Correspondence Points: Ports: VDD DINP DINN CLK180 CLK0 CLK270 CLK90 VSS DOUT1P DOUT0N DOUT0P DOUT1N irefpnxor2 irefpnxor1 DOWNP DOWNN UPP UPN CELL COMPARISON RESULTS # ################### _ _ # # # * * # # # CORRECT # | # # # # \___/ # ################### LAYOUT CELL NAME: CDR SOURCE CELL NAME: CDR -------------------------------------------------------------------------------------------------------------- NUMBERS OF OBJECTS ------------------ Layout Source Component Type ------ ------ -------------- Ports: 20 20 Nets: 52 52 Instances: 2 2 COMP2 (8 pins) 1 1 CP2 (10 pins) 1 1 PI_CTRL (20 pins) 1 1 REFGEN (11 pins) 1 1 VI3 (7 pins) 2 2 PI_CLKBUF (13 pins) 1 1 PD (18 pins) ------ ------ Total Inst: 9 9 ************************************************************************************************************** INFORMATION AND WARNINGS ************************************************************************************************************** Matched Matched Unmatched Unmatched Component Layout Source Layout Source Type ------- ------- --------- --------- --------- Ports: 20 20 0 0 Nets: 52 52 0 0 Instances: 2 2 0 0 COMP2 1 1 0 0 CP2 1 1 0 0 PI_CTRL 1 1 0 0 REFGEN 1 1 0 0 VI3 2 2 0 0 PI_CLKBUF 1 1 0 0 PD ------- ------- --------- --------- Total Inst: 9 9 0 0 o Initial Correspondence Points: Ports: clkbuf180 clkbuf0 clkbuf90 clkbuf270 VDDD VSS VDDA clk180 clk270 datainp datainn clk90 clk0 vrefcp iref25np200u iref01np200u dataout1n dataout1p dataout0p dataout0n CELL COMPARISON RESULTS ( TOP LEVEL ) # ################### _ _ # # # * * # # # CORRECT # | # # # # \___/ # ################### Warning: Ambiguity points were found and resolved arbitrarily. LAYOUT CELL NAME: CHIP SOURCE CELL NAME: CHIP -------------------------------------------------------------------------------------------------------------- NUMBERS OF OBJECTS ------------------ Layout Source Component Type ------ ------ -------------- Ports: 1 1 Nets: 21 21 Instances: 17 17 PPX_ANA_LIN (0 pins) 2 2 VDDIOCO_1V0_ANA_LIN2 (0 pins) 1 1 VSSIOCO_1V0_ANA_LIN2 (0 pins) 1 1 CDR (20 pins) ------ ------ Total Inst: 21 21 ************************************************************************************************************** INFORMATION AND WARNINGS ************************************************************************************************************** Matched Matched Unmatched Unmatched Component Layout Source Layout Source Type ------- ------- --------- --------- --------- Ports: 1 1 0 0 Nets: 21 21 0 0 Instances: 17 17 0 0 PPX_ANA_LIN 2 2 0 0 VDDIOCO_1V0_ANA_LIN2 1 1 0 0 VSSIOCO_1V0_ANA_LIN2 1 1 0 0 CDR ------- ------- --------- --------- Total Inst: 21 21 0 0 o Initial Correspondence Points: Ports: esdsub ************************************************************************************************************** SUMMARY ************************************************************************************************************** Total CPU Time: 1 sec Total Elapsed Time: 1 sec