ECE1388 Final Project

December 23, 2016

Christos Konstantopoulos 1002500386

Zhe Gong 998067595

Mojtaba Ashourloo 1001033446

Note: layout images have been removed for IP reasons. Please contact one of the authors for information.

Zhe Gong:

zhe.gong@mail.utoronto.ca

Mojtaba Ashourloo:

mojtaba.ashourloo@mail.utoronto.ca

Christos Konstantopoulos:

c.konstantopoulos@mail.utoronto.ca

Introduction

With the widespread adoption of light-emitting diode (LED) technologies for automotive light fixtures, it has recently been proposed that automobiles could send information to each other through a technique known as visible light communication (VLC) [1]-[2]. Visible light communication involves the switching of lights at frequencies above a certain threshold to transmit information without apparent disruption to the environment. Some examples of on-road VLC applications are shown in Figure 1. Light-emitting diodes have the capability to switch in the megahertz frequency range, making them a good candidate for VLC application, but existing integrated power solutions do not fully support the application. In this project, the goals were to gain design experience, and to build the foundation of what will become a VLC-supporting LED power module IC for the automotive environment.

Figure 1: Possible on-road applications of VLC [1].

Project Scope

It is assumed that the LED module at the converter output will be a string of series-connected white LEDs operating at a nominal voltage of 60 V. The power available to electronics in a typical automobile comes from the 12 V auxiliary DC bus. Due to these voltage levels, a converter with boost functionality is required. The basic boost topology was chosen in this project. Full specifications for the IC are given in Table 1.

In the end application, VLC will require the LEDs to be toggled at a high frequency, so the converter control have fast reaction time. To fulfill this requirement, a switching speed of 1 MHz and peak current control were chosen. An off-time generator was implemented for fixed-frequency operation in the presence of input and output voltage disturbances [3].

Table 1: Boost converter power module specifications

Input voltage	12 V
Output voltage	60 V
Output power	12 W
Chip efficiency	97 %
Switching frequency	1 MHz
Inductance	100 µH
Output capacitance	10 µF
Supply voltage	5 V
Chip package	SO-16
Process technology	Magnachip 80V BCD

To reduce project complexity, it was decided that the boost converter’s high-side switch would be a diode, and only the low-side MOSFET would be implemented on-chip. Changing the high-side switch to a diode removes the need for level-shifting to drive a high-side gate. Due to the poor diode performance of the process used, removing the diode from the chip improves the overall system performance

Converter Design

The converter block diagram is shown in Figure 2. To begin the design, the converter and controller were simulated in the PLECS simulation package in order to verify system-level functionality. Figures 3 and 4 show the schematic and steady state operation, respectively.

Figure 2: Boost converter block diagram. On-chip items are enclosed in dotted boxes.

Figure 3: Boost converter simulation schematic

Figure 4: Simulated steady-state converter operation

Chip Design

The chip design was initiated by the creation of a floor plan, which is shown in Figure 5. This was followed by schematic design of the various analog components, a system-level simulation in Cadence (Figure 6), and then layout. Figures 7-8 show the power MOSFET and sizing analysis. Figures 9-20 contain exported schematic and layouts of the control system blocks. Figure 21 contains the DRC report and Figure 22 contains the LVS report, both for the top-level layout. Aside from metal density rules, all components have passed the checks.

Figure 5: Chip floor plan

Figure 6: System-level simulation in Cadence using same parameters as in PLECS

Figure 7: Top-level chip layout with pad ring. The biggest component is the power MOSFET (centre square).

Figure 7 highlights the relatively large size of the power MOSFET compared to the other system components. The primary constraint in the power MOSFET design is the amount of losses inside, all of which will be dissipated as heat during operation. The design for the MOSFET was thus based on thermal limits of the SO16 package [4]. Specifically, the R_ds,on and Q_gate were characterized, and the following equations were used to calculate the power dissipation in the gate driver and switch.

Figure 8 shows the simulations performed in order to characterize the power MOSFET. It was found that about 235 mW of power would be dissipated on chip, which is well below the 3.42 W limit assuming a junction-to-case thermal resistance of 36.5 ^oC/W and a junction temperature limit of 150 ^oC. It must be noted that this analysis does not include the switching losses, which are dependent on the switch output capacitance and converter operating conditions.

Figure 8: Characterization tests for R_ds,on (left) and Q_gate (right). The simulated values are R_ds,on = 100 mOhm and Q_gate = 4 nC.

A current-sense MOSFET was also designed into the power MOSFET, which is a current mirror roughly biased to match the main power MOSFET during the on-phase of the switching cycle and ignored during the off-phase of the switching cycle. The accuracy of this sensor is important to the correct operation of the converter with controller in closed-loop.

Figure 9: DIfferential comparator schematic

Figure 10: Differential comparator layout

Figure 11: Operational transconductance amplifier schematic

Figure 12: Operational transconductance amplifier layout

Figure 13: Off-time generator schematic. This block includes one OTA, one PMOS feedback resistor, a current mirror to act as a current source, and the timing capacitor and a discharge switch. The capacitor charge current is controlled by an external resistor.

Figure 14: Off-time generator layout

Figure 15: Bias current generator schematic

Figure 16: Bias current generator layout

Figure 17: RS latch schematic

Figure 18: RS latch layout

Figure 19: Sense MOSFET voltage amplifier schematic

Figure 20: Sense MOSFET voltage amplifier layout

Design Rule Check

****NOTE****************************************************************************

As will be seen below, there are several DRC rules that were not met (highlighted). These are metal layer density rules that were ignored since the design will change in the future.

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Layout Versus Schematic

References

[1] http://spectrum.ieee.org/transportation/advanced-cars/leds-bring-new-light-to-car-to-car-communication

[2] S. Zhao, J. Xu and O. Trescases, "Burst-Mode Resonant LLC Converter for an LED Luminaire With Integrated Visible Light Communication for Smart Buildings," in IEEE Transactions on Power Electronics, vol. 29, no. 8, pp. 4392-4402, Aug. 2014.

doi: 10.1109/TPEL.2013.2286104

[3] Y. Zhang, H. Chen and D. Ma, "A V_O -Hopping Reconfigurable RGB LED Driver With Automatic \Delta V_O Detection and Predictive Peak Current Control," in IEEE Journal of Solid-State Circuits, vol. 50, no. 5, pp. 1287-1298, May 2015.

[4] “IC Design of Power Management Circuits (I)”, Wing-Hung Ki, International Symposium on Integrated Circuits, Dec. 14, 2009