Transistor Level Design of

RF and High-Speed Integrated Circuits

for Wireless, Optical Fiber and Back Plane Communications

Instructor: Sorin Voinigescu

Room: BA5132, E-mail sorinv@eecg.toronto.edu

Course Description

A design intensive overview of high-speed and RF monolithic integrated circuits for wireless and optical fiber systems with an emphasis on device-circuit topology interaction and optimization. Noise, high-frequency common-mode and differential-mode stability and matching, methodologies for maximizing circuit bandwidth, as well as layout and isolation techniques will be discussed. Students will participate in a group project on RF or optical fiber circuits using advanced RF CMOS and SiGe BiCMOS technologies.

Grading Scheme:

40% midterm (open book)

30% assignments (10% each)

30% project

Objectives: to familiarize the graduate student with:

• the main RF and optical fiber system architectures and their requirements,

• circuit building blocks and the issues related to device-circuit interaction at very high frequencies;

• "the active and passive device design is part of the circuit design" philosophy;

• transistor-level building block design of: VCOs, LNAs, Mixers, Transimpedance Amplifiers, Laser/Modulator Drivers and 50-Ohm I/O Drivers,

• transistor bias and geometry design for optimal speed, maximum linearity and/or minimum noise,

• inductor and transmission line modelling and design in single-ended and differential topologies,

• layout design techniques to improve on-chip isolation at very high frequencies.

• State-of-the art Si CMOS and SiGe BiCMOS technologies used in very high-speed ICs

Topic Outline

RF and Optical Fiber Systems. Typical system architectures. Definition of main design parameters for RF and optical fiber systems. RF & high-speed design vs. analog design. Noise Figure and Sensitivity. Two-port noise parameters in the presence of noise correlation. Eye diagrams and jitter. Linearity issues: P_o1, IIP3, IIP2.

High-Frequency Active and Passive Device Modelling and Design. RF models and parameter extraction techniques for Si MOSFETs and SiGe HBTs. Transistor cutoff frequency, maximum oscillation frequency, noise figure and noise parameters. Transistor biasing and sizing for optimal high-speed and low-noise operation. High-frequency models and parameter extraction techniques for varactors, inductors, and transmission lines. Design and analysis of inductors and transformeres using ASITIC.

Noise and Matching Techniques in High-Frequency Circuits. The theory of noise in feedback circuits. Noise parameters of circuits with parallel-parallel feedback. Transimpedance amplifier example. Noise parameters of circuits with series-series feedback. Differential stage example. Input and output matching. Inter-stage matching. high-frequency issues in differential circuits and coupled transmission lines. Common-mode vs. differential-mode vs. single-ended matching and stability.

Tuned and Broadband Circuit Topologies and Design Methodologies. Design methodology for tuned low-noise amplifiers, mixers and low-noise monolithic VCOs. Techniques for broadband design: buffering and scaling, Cherry Hooper stage, f_T doubler, inductive peaking, distributed amplifier. Topologies and design methodology for high-speed logic families: SiGe BiCMOS CML, ECL, and E²CL, and CMOS-CML. Techniques for wave-shape control in high-speed I/Os. Pulse-width, output amplitude and pre-emphasis control. Design methodology for 50-Ohm output drivers. Design methodology for broadband low-noise transimpedance amplifier. High-frequency layout and isolation techniques.

Assignments (3)

1. Simulation of high-frequency (cutoff frequency, maximum frequency of oscillation, peak f_T and f_MAX bias) and noise characteristics (minimum noise figure, optimum noise impedance, optimal noise bias) of Si MOSFETs and SiGe HBTs f_T(I_C/I_D), f_T(V_CE/V_DS), f_MAX(I_C/I_D), f_MAX(V_CE/V_DS), NF_MIN(I_C/I_D), NF_MIN(V_CE/V_DS), R_OPT(I_C/I_D), Ropt(V_CE/V_DS). Device geometry scaling study: f_T, f_MAX, NF_MIN. Extraction of the small-signal equivalent circuit parameters from measured/simulated data. Spectre and/or Hspice will be used.

2. Design and simulation of the high-frequency characteristics (L(f), Q(f)) of a two-terminal inductor and of a transformer using ASITIC. Extraction of the equivalent circuit parameters from the simulated (measured) Z(f) and Y(f) parameters.

3. Design of tuned and broadband Low-Noise Amplifiers using RF CMOS and SiGe BiCMOS technologies.

Project (groups of two students)

The project involves the design and schematic-level simulation and analysis of a circuit similar to the ones below from previous years:

1. 2-to-10 GHz UWB radio receiver in 65-nm CMOS (LNA, Mixer, synthesizer)

2. 24-GHz automotive collision avoidance radar in 65-nm CMOS (VCO, PA, image-reject mixer, pulse modulator, antenna switch, synthesizer)

3. 48-Gb/s optical fiber equalizer in 65-nm CMOS (3-tap FFE, 1-tap DFE, 1:4 DMUX, full-rate CDR)

4. 48-Gb/s, 50-Ohm I/O Driver with adjustable wave shape (output swing, pulse-width and pre-emphasis control) in 65-nm CMOS.

5. 60-GHz WLAN 4´transmitter phased array in 65-nm CMOS (VCO, PA, phase-shifter divider)

6. 60-GHz WLAN 4´ receiver phased array in 65-nm CMOS (LNA, phase-shifter, VCO, image-reject mixer)

7. 100-Gb/s receiver with equalization in SiGe BiCMOS process (3-tap FFE, 1-tap DFE 1:4 DMUX, half-rate CDR)

8. 110-GB/s 50-Ohm, 4V differential driver with adjustable wave shape (output swing, pulse-width and pre-emphasis control) using an advanced SiGe BiCMOS process.

9. 120-GHz 4´receiver phased-array using an advanced SiGe BiCMOS process (LNA, phase-shifter, VCO, image-reject mixer+antenna)

10. 120-GHz 4´transmitter phased-array using an advanced SiGe BiCMOS process (PA, phase-shifter, VCO, single sideband mixer+antenna)

The project requires two reports:

1. General specification (GS) based on initial input from instructor, literature survey of similar circuits and initial feasibility study.

2. Circuit Description (CD)

and a 25-minute oral presentation in front of the class.

The CD will cover:

• Block diagram and schematics of all building blocks.

• Design considerations, design methodology, and hand design equations.

• Equivalent circuit and simulation results for the frequency response of all the inductors, transformers, and transmission lines used in the design.

• DC, S parameter and transient simulation results of the entire circuit and building blocks (if appropriate). All parameters specified in the GS must be simulated over temperature and bias supply corners (and process corners if available).

• An explanation must be provided for the parameters that do not meet the initial GS.

• Brief description of test bench setup and test methodology for HF and/or high-speed parameter in the GS.

The CD must contain sufficient information for another engineer to be able to reproduce your circuit design and/or to be able to test it in the lab.

The project mark will be based on the performance of your circuit, the thoroughness of the CD, the degree to which you have been able to meet the original GS and the quality of the oral presentation.

References (primary):

1. Lecture notes

2. "Broadband Circuits for Optical Fiber Communication”, by Eduard Sackinger, 2005

3. “Microwave Engineering”, 3^rd. Edition, by David Pozar, John Wiley, 2005.

4. A.M. Niknejad ASITIC user manual.

5. T.O. Dickson, M.-A. LaCroix, S. Boret, D. Gloria, R. Beerkens, and S.P. Voinigescu, “30-100 GHz Inductors and Transformers for Millimeter-wave (Bi)CMOS Integrated Circuits”, IEEE Trans. MTT, Vol.53, No.1, pp.123-133, 2005.

6. S.P. Voinigescu, M. C. Maliepaard, J. L. Showell, G. Babcock, D.Marchesan, M. Schroter, P.Schvan, and D. L. Harame, "A Scalable High-Frequency Noise Model for Bipolar Transistors with Application to Optimal Transistor Sizing for Low-Noise Amplifier Design", IEEE Journal of Solid-State Circuits, Vol.32, No.9, pp.1430-1438, 1997.

7. T.O. Dickson, K.H.K. Yau, T. Chalvatzis, A. Mangan, R. Beerkens, P. Westergaard, M. Tazlauanu, M.T Yang, and S. P. Voinigescu, “The Invariance of Characteristic Current Densities in Nanoscale MOSFETs and its Impact on Algorithmic Design Methodologies and Design Porting of Si(Ge) (Bi)CMOS High-Speed Building Blocks,” IEEE Journal of Solid-State Circuits, vol. 41, no. 8, pp. 1830-1845, Aug. 2006.

8. M.A.Copeland, S.P.Voinigescu, D.Marchesan, P.Popescu, and M.C.Maliepaard ,"5 GHz SiGe HBT Monolithic Radio Transceiver With Tunable Filtering," IEEE Trans. on MTT, Vol. 48, No.2, pp.170-181, Feb. 2000.

9. Other papers from JSSC, IEEE Trans on. MTT, RFICS, IMS, ISCC, BCTM, CSICS.

References (secondary)

1. "The Design of CMOS Radio-Frequency Integrated Circuits" by T.H. Lee, Cambridge University Press, 2004.

2. Design of Integrated Circuits for Optical Communications,” by Behzad Razavi, McGraw Hill, 2003.