This paper describes the polymorphous TRIPS architecture which can be
configured for different granularities and types of parallelism. TRIPS contains
mechanisms that enable the processing cores and the on-chip memory system to be
configured and combined in different modes for instruction, data, or
thread-level parallelism. To adapt to small and large-grain concurrency, the
TRIPS architecture contains four out-of-order, 16-wide-issue Grid Processor
cores, which can be partitioned when easily extractable fine-grained
parallelism exists. This approach to polymorphism provides better performance
across a wide range of application types than an approach in which many small
processors are aggregated to run workloads with irregular parallelism. Our
results show that high performance can be obtained in each of the three
modes---ILP, TLP, and DLP---demonstrating the viability of the polymorphous
coarse-grained approach for future microprocessors.