Greg Steffan

Associate Professor &
Jeffrey Skoll Chair in
Software Engineering
ECE, U of Toronto

It is with deep sadness that we
announce Professor Greg Steffan's
passing on July 24, 2014.

Research Team
Pubs (by type)
Pubs (by date)
Reading Group

Downloads: Released Resources

DART: An FPGA-Based Network-on-Chip Simulation Acceleration Engine

DART is an FPGA implementation of a network-on-chip simulator, where the topology and parameters of the simulated network can be modified without rebuilding the FPGA image. DART is described in our NOCS 2011 paper, and is available for download.

Multi-Ported Memories for FPGAs

FPGA fabrics typically contain block-memories that provide only two ports; if you require a memory with more than two ports then there are several ways to construct them depending on your desired speed/area trade-off, as described in our FPGA 2010 paper Efficient Multi-Ported Memory Implementations for FPGAs. Our designs are available for download.

VESPA: Parameterized FPGA-Based Vector Processor

VESPA is an FPGA-based vector processor that implements the Berkeley VIRAM ISA. The hardware design source, compiler/assembler, simulator, and example applications are available for download

NetThreads and NetTM: Multithreaded Multiprocessors for the NetFPGA Platform

NetThreads allows the NetFPGA platform to be programmed via multithreaded software that synchronizes and shares memory, allowing the implementation of deeper packet inspection workloads. Available for download are the hardware design source for NetThreads and NetThreads-RE (the "Router Edition", optimized for routing applications). Also available is NetTM, an improved version of NetThreads that supports Transactional Memory as well as lock-based critical sections, for easing synchronization and improving parallel overlap of threads. We have also released the Caliper precise traffic generation system for NetFPGA+NetThreads.

SPREE: an FPGA-Based Soft Processor Generator

SPREE (Soft Processor Rapid Exploration Environment) can be used to generate MIPS-compatible FPGA-based soft processors, and comes with compiler and example processor designs.

Power-Law Network Topology Generator Software

As described in our Globecom 2000 paper, this source code implements the PLODD and Recursive topology generators. Please see the README for more info.