Paper Details
Reference:
David Tam, Reza Azimi, Livio Soares, and Michael Stumm,
"RapidMRC: Approximating L2 miss rate curves on commodity systems for online optimizations",
In Proceedings of the 14th International Conference on Architectural Support for Programming Languages & Operating Systems (ASPLOS'09), Washington, DC, USA, ACM, New York, NY, USA, March, 2009, pp. 121–132.
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Abstract:
Miss rate curves (MRCs) are useful in a number of contexts. In our research, online L2 cache MRCs enable us to dynamically identify optimal cache sizes when cache-partitioning a shared-cache multicore processor. Obtaining L2 MRCs has generally been assumed to be expensive when done in software and consequently, their usage for online optimizations has been limited. To address these problems and opportunities, we have developed a low-overhead software technique to obtain L2 MRCs online on current processors, exploiting features available in their performance monitoring units so that no changes to the application source code or binaries are required.
Our technique, called RapidMRC, requires a single probing period of roughly 221 million processor cycles (147 ms), and subsequently 124 million cycles (83 ms) to process the data. We demonstrate its accuracy by comparing the obtained MRCs to the actual L2 MRCs of 30 applications taken from SPECcpu2006, SPECcpu2000, and SPECjbb2000. We show that RapidMRC can be applied to sizing cache partitions, helping to achieve performance improvements of up to 27%.
Keywords:
operating systems, cache management, cache partitioning, chip multiprocessor, dynamic optimization, hardware performance counters, miss rate curve, multicore processor, online optimization, performance monitoring unit, shared cache, shared cache management
Reference Info:
DOI: 10.1145/1508244.1508259
ACMid: 1508259
ISBN: 978-1-60558-406-5
ISSN: 1523-2867
OCLC: 429098628
BibTeX:
@inproceedings(Tam-ASPLOS09,
author = {David Tam and Reza Azimi and Livio Soares and Michael Stumm},
title = {{RapidMRC}: {Approximating L2} miss rate curves on commodity systems for online optimizations},
booktitle = {Proceedings of the 14th International Conference on Architectural Support for Programming Languages & Operating Systems (\textbf{ASPLOS'09})},
location = {Washington, DC, USA},
organization = {ACM},
address = {New York, NY, USA},
month = {March},
year = {2009},
pages = {121-132},
doi = {10.1145/1508244.1508259},
isbn = {978-1-60558-406-5},
issn = {1523-2867},
keywords = {operating systems, cache management, cache partitioning, chip multiprocessor, dynamic optimization, hardware performance counters, miss rate curve, multicore processor, online optimization, performance monitoring unit, shared cache, shared cache management}
)