The "FPGA Place-and-Route Challenge"

To encourage FPGA researchers to benchmark their CAD tools on large circuits, we have created an "FPGA Place-and-Route Challenge." For every track by which a researcher reduces the total number of tracks required to route these circuits (from the previously best total number of 177) we will pay him/her $1! (Sorry, $1 Cdn, not $1 U.S.)

The number of tracks in a routing channel is simply the number of wires that may be used in that channel (i.e. the "width" of the channel). The total number of tracks required to route the 20 benchmark circuits is simply the sum over all 20 circuits of the minimum channel width required to successfully route each circuit.

Current and Historical Champions

-place_algorithm bounding_box -max_router_iterations 100 -pres_fac_mult 1.5 -router_algorithm breadth_first

This makes VPR use its wirelength-driven placement and routing algorithm, and makes the router work somewhat harder than usual. The sum of the track count needed to route each circuit is 177 tracks. The CPU times are still quite reasonable; the time to place and repeatedly route each circuit averages about 3 hours on a fairly obselete 300 MHz Ultrasparc processor.

Past record holders are the combination of VPR to place a circuit and SC-Pathfinder to route the circuit (total 188 tracks) and VPR version 3.99 with default placement and routing effort (total 194 tracks).

The FPGA Architecture

Click here to see all the details of the FPGA architecture your tools must target. Read these rules carefully and make sure your tools are targetting the architecture exactly! Otherwise, your results won't be comparable to those of other researchers and we won't be able to accept them.

If you want to run VPR on this architecture, click here to get the .arch file describing this architecture in VPR format.

The Benchmark Circuits

Press the green button to download the specified item.

Download the .net format netlists of the twenty large MCNC circuits used as benchmarks for the place-and-route challenge.

Download the placements produced by VPR 4.30, wirelength-driven placement algorithm with default effort, for the twenty large circuits above. (You only need these placements if your CAD tool does only routing, rather than both placement and routing.)

Click here to read a description of the circuit netlist format and the placement file format.

Other Documentation, Rules, and Reporting Results

To send in valid results for the challenge, you must:

• Send us a table listing the track count your CAD tool achieves for each benchmark circuit.
• Send us at least an executable copy of the program used to generate the results. We can run Solaris or Windows NT executables.
• Your program must use the same command-line options to place and route all the circuits (no command line or algorithm tweaking on a circuit-specific basis).
• Your program must output the final placement (if it is a placement tool) and/or routing (if it is a routing tool) of each circuit. We will use this output to make sure the targetted FPGA architecture is exactly correct, and that the placement and routing is fully legal. Ideally, the output would mimic the .p (placement) and .r (routing) formats used by VPR, but if that's too hard, any ASCII output format (accompanied by proper documentation) will do.
• We haven't put a hard CPU limit on the contest, but your CPU time should be reasonable. If it takes weeks for me to reproduce your results, you have probably gone off the deep end on CPU time. I won't accept results that involve simply turning up the optimization parameters on VPR. Anyone can reduce track count slightly just by burning a lot more CPU time in VPR, but that just turns into a competition to see who is willing to burn the most CPU.

Results

The table below shows the size of the 20 benchmark circuits, in terms of a 4-LUT + flip flop logic block, and the number of tracks required to successfully place and route each by CAD tools for which we have results.

Benchmark circuits and track counts

Circuit	Size (Logic Blocks)	VPR 3.99 Tracks	SEGA Tracks*	SC-Pathfinder Tracks**	VPR 4.30 Tracks***
alu4	1522	10	16	9	9
apex2	1878	11	20	11	10
apex4	1262	12	19	11	11
bigkey	1707	7	9	6	6
clma	8383	12	25	12	10
des	1591	7	11	7	7
diffeq	1497	7	10	7	7
dsip	1370	7	9	6	5
elliptic	3604	10	16	9	9
ex1010	4598	10	22	10	9
ex5p	1064	13	16	12	11
frisc	3556	11	18	11	11
misex3	1397	10	17	10	10
pdc	4575	16	33	16	15
s298	1931	7	18	7	6
s38417	6406	8	10	7	6
s38584.1	6447	9	12	8	7
seq	1750	11	18	11	10
spla	3690	13	26	12	12
tseng	1407	6	9	6	6
Total:	--	197	334	188	177

*SEGA performs detailed routing only, so VPR was used to place and globally route the circuits. SEGA was then used for detailed routing.

**SC-Pathfinder is a routing tool only, so VPR was used to generate the placement for each circuit. SC-Pathfinder was then used to perform a combined global-detailed routing.

***VPR 4.30 run in wirelength-driven mode for placement and routing, with increased routing effort. Command line: -place_algorithm bounding_box -max_router_iterations 100 -pres_fac_mult 1.5 -router_algorithm breadth_first