Title:
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Parallel CAD for FPGAs: A Personal Retrospective and Thoughts for the Future


Abstract:
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For decades, FPGA capacity and processor performance both increased due to Moore's Law, helping keep CAD runtimes reasonable despite ever-larger designs. In approximately 2006, this relationship started to break down, raising the spectre of the already significant FPGA compile times becoming intolerable as FPGA capacity grew. From that realization grew Altera's effort to make all their major CAD algorithms parallel, despite the complexity of speeding up multiple highly-tuned and complex algorithms that together comprised millions of lines of code.

In this talk I will discuss the motivation for this project, and how it led to internal rules for deterministic algorithms to keep debugging tractable. The Quartus parallel placement algorithm was published in FPGA 2008 and was one of a suite of algorithms that together enabled the first parallel compile CAD tool in the FPGA industry. Since that date parallel compile and requirements for deterministic algorithms have become standard throughout the industry, and multiple enhancements to parallel placement and other parallel CAD stages have been published and productized. 

Despite this helpful and necessary progress, compile times remain a major issue. We will conclude the talk with some open questions on how much current algorithms can be sped up with parallelism, and some thoughts on design flow and architecture changes that can increase parallelism and thereby enable faster design cycles.

Speaker Bio:
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Vaughn Betz is the original developer of the widely used VPR FPGA placement, routing and architecture evaluation CAD flow. He co-founded Right Track CAD to commercialize VPR, and joined Altera upon its acquisition of Right Track CAD. Dr. Betz spent 11 years at Altera, ultimately as Senior Director of software engineering, and is one of the architects of the Quartus II CAD system and the first five generations of the Stratix and Cyclone FPGA families. He is currently a professor and the NSERC/Intel Industrial Research Chair in Programmable Silicon at the University of Toronto. He holds 100 US patents and has published over 100 technical articles in the FPGA area. Thirteen of these papers have won best or most significant paper awards, including the FPGA 2008 paper on Efficient and Deterministic Parallel Placement for FPGAs that forms the back story for this talk.