One type of highly programmable chip is a Field Programmable Gate Array (FPGA). In these devices, a large number of programmable function blocks are connected by programmable routing. The processing performed by each function block can be changed by loading a different set of bits, or "configuration" in the function block, and the connections between function blocks are made by transistor-based switches, rather than fixed wires, allowing the wiring between blocks to be changed by loading a different programming configuration. Taken together, these two forms of reprogrammability allow any desired circuit to be implemented in an FPGA, without any need for the design and manufacture of a custom chip. FPGAs have become very important devices: their sales are over $5 billion per year, and they are used in very diverse markets ranging from high-end communications equipment to children's electronic games.
The reprogrammability of an FPGA comes at a cost, however: circuits implemented in FPGAs are larger (and hence more costly), slower and more power-hungry than those implemented in a custom computer chip. My research encompasses finding new architectures for Field Programmable Gate Arrays (FPGAs) to improve their speed, cost and power, improving the Computer-Aided Design (CAD) tools that are used to automatically implement applications in FPGAs, and developing new, faster systems and applications targeting FPGAs.
There are many interesting challenges in each of these 3 areas. Finding better FPGA architectures involves finding both better function blocks that can implement more logic (or other) functionality in the same area and power, and choosing the right function blocks to add to an FPGA. The programmable interconnect that ties these function blocks together adds several major challenges of its own: how should the wires and switches be arranged to make the most efficient network, and how should the low-level circuitry that forms the programmable routing be designed?
The CAD tools used to automatically implement designs in FPGAs present another very interesting set of research problems. There are many computational difficult tasks involved in the FPGA CAD flow, including synthesis of the function blocks to implement the desired circuit, placement of the hundreds of thousands or millions of function blocks to minimize the wiring and delay between blocks that must communicate to implement the design, and routing the millions of connections between these blocks by configuring the pre-fabricated switches forming the FPGA routing architecture. Creating better and faster CAD tools includes many techniques, including finding better heuristic optimization algorithms, creating parallel algorithms that still achieve high result quality, and even defining entirely new CAD flows that can make designers more productive by raising the level of design abstraction.
Many computations can be sped up with FPGA hardware, including signal processing, communication coding/decoding, packet processing, and scientific computation. My interest in FPGA applications is two-fold: (1) finding ways to leverage the unique capabilities of FPGAs to speed-up new applications and (2) developing high-quality implementations of key applications that can be used to inform (by examining the application bottlenecks) and test (by using the application as a benchmark) research into better FPGA architectures and CAD tools.
In addition to researching ways to make traditional FPGAs and CAD tools better, my research also includes finding new, hybrid devices that incorporate both FPGA technologies (such as programmable routing and logic) and aspects of other programmable devices, such as processor cores and packet processing units. The goal is to create hybrid devices that are better suited to some key applications -- for example, the very highly parallel portions of a wireless communication system may map best to a hardware pipeline built in a conventional FPGA fabric, while the more complex control flow would map to processor cores embedded in the device.
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