module hardware_fifo (
	clk,
	reset,
	read,
	write,
	writedata,

	readdata,
	wait_read,
	wait_write);
	
input			clk;
input			reset;
input			read;
input			write;
input [31:0]	writedata;

output [31:0]	readdata;
output			wait_read;
output			wait_write;
parameter	fifo_depth = 4,
			data_width = 32;

scfifo	the_fifo (
	.rdreq (read & ~wait_read),
	.aclr (reset),
	.clock (clk),
	.wrreq (write & ~wait_write),
	.data (writedata),
	
	.empty (wait_read),
	.q (readdata),
	.full (wait_write),
	
	.almost_empty (),
	.almost_full (),
	.sclr (),
	.usedw ()
);
defparam
	the_fifo.add_ram_output_register = "OFF",
	the_fifo.lpm_numwords = fifo_depth,
	the_fifo.lpm_showahead = "ON",
	the_fifo.lpm_type = "scfifo",
	the_fifo.lpm_width = data_width,
	the_fifo.lpm_widthu = 2,
	the_fifo.overflow_checking = "OFF",
	the_fifo.underflow_checking = "OFF",
	the_fifo.use_eab = "ON";

	
	
endmodule
