// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 
<REPLACE_THIS>                                                                                                                                                                                                                                                                                                          
(
                                 // inputs:
                                  clk,
                                  read,
                                  reset,
                                  write,
                                  writedata,

                                 // outputs:
                                  readdata,
                                  wait_read,
                                  wait_write
                               )
;

  output  [ 31: 0] readdata;
  output           wait_read;
  output           wait_write;
  input            clk;
  input            read;
  input            reset;
  input            write;
  input   [ 31: 0] writedata;

  wire    [ 31: 0] readdata;
  wire             wait_read;
  wire             wait_write;
  hardware_fifo the_hardware_fifo
    (
      .clk        (clk),
      .read       (read),
      .readdata   (readdata),
      .reset      (reset),
      .wait_read  (wait_read),
      .wait_write (wait_write),
      .write      (write),
      .writedata  (writedata)
    );
  defparam the_hardware_fifo.data_width = 32,
           the_hardware_fifo.fifo_depth = 4;


endmodule

