Conference Papers (since 1990)

1. F. Plavec, Z.G. Vranesic and S.D. Brown, "Enhancements to FPGA design methodology using streaming", Proc. FPL 2009, pp. 294-301.

2. F. Plavec, Z.G. Vranesic and S.D. Brown, "Towards Compilation of Streaming Programs into FPGA Hardware", Proc. FDL 2008, Stuttgart, Germany, Sep. 2008, pp. 67-72.

3. F. Plavec, Z.G. Vranesic and S.D. Brown, "On Digital Search Trees: A Simple Method for Constructing Balanced Binary Trees", Proc. ICSOFT '07, Barcelona, Spain, July 2007, pp. 61-68.

4. V. Manohararajah, S.D. Brown and Z.G. Vranesic, "Adaptive FPGAs: High-Level Architecture and a Synthesis Method", Proc. FPLA, Madrid, Spain, Aug. 2006, pp. 267-274.

5. B. Fort, D. Capalija, Z.G. Vranesic and S.D. Brown, "A Multithreaded Soft Processor for SoPC Area Reduction", Proc. ISCCM 2006, Napa, CA. Oct. 2006, pp. 131-142.

6. F. Plavec, B. Fort, Z.G. Vranesic and S.D. Brown, "Experiences with Soft-Core Processor Design", IPDPS 2005.

7. V. Manohararajah, S.D. Brown and Z.G. Vranesic, "Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping", Proc. International Workshop on Logic and Synthesis, (IEEE), Temecula, Ca., June 2004, pp. 14-21.

8. V. Manohararajah, T. Borer, S.D. Brown and Z.G. Vranesic, "Automatic Partitioning for Improved Placement and Routing in Complex Programmable Logic Devices", FPL 2002, Montpelier, France, Sept. 2002, pp. 232-241.

9. R. Grindley, T. Abdelrahman, S. Brown, S. Caranci, D. DeVries, B. Gamsa, A. Grbic, M. Gusat, R. Ho, O. Krieger, G. Lemieux, K. Loveless, N. Manjikian, P. McHardy, S. Srbljic, M. Stumm, Z. Vranesic and Z. Zilic, "The NUMAchine Multiprocessor", Proc. 2000 Int. Conf. on Parallel Processing, (IEEE/IACC), Toronto, Ont., Aug. 2000, pp. 487-496.

10. Z.G. Vranesic, "A Computer Architect's View of Photonic Interconnects", (invited talk), Proc. Optics in Computing, OSA Conference, Aspen, Colorado, Apr. 1999, pp. 144-145.

11. A. Grbic, S. Brown, S. Caranci, R. Grindley, M. Gusat, G. Lemieux, K. Loveless, N. Manjikian, S. Srbljic, M. Stumm, Z. Vranesic and Z. Zilic, "Design and Implementation of the NUMAchine Multiprocessor", Proc. Design Automation Conf., (IEEE/ACM), San Francisco, CA., June 1998, pp. 66-69.

12. Z.G. Vranesic, "The FPGA Challenge", Proc. 28th Int. Symp. on Multiple-Valued Logic, Fukuoka, Japan, May 1998, pp. 121-126.

13. K. Farkas, P. Chow, N. Jouppi, and Z. Vranesic, "The Multicluster Architecture: Reducing Cycle Time Through Partitioning", In The 30th Annual International Symposium on Microarchitecture: MICRO-30, (IEEE/ACM), Research Triangle Park, NC., Dec. 1997, pp. 149-159.

14. K.I. Farkas, P. Chow, N.P. Joupi and Z.G. Vranesic, "Memory-system Design Considerations in Dynamically-schedulled Processors", Proc. 24th International Symposium on Computer Architecture, (IEEE), Denver, Colorado, June 1997, pp. 133-143.

15. S. Wilton, J. Rose, Z. Vranesic, "Memory-to-Memory Connection Structures in FPGAs with Embedded Memory Arrays", Proc. FPGA '97, ACM Symp. on FPGAs, Feb. 1997, pp. 10-16.

16. S.J.E. Wilton, J. Rose and Z.G. Vranesic, "Memory/Logic Interconnect Flexibility in FPGAs with Large Embedded Memory Arrays", Proc. IEEE Custom Integrated Circuits Conf., May 1996, pp. 144-147.

17. S. Brown, N. Manjikian, Z. Vranesic, R. Grindley and K. Loveless, "Experience in Designing a Large-scale Multiprocessor using Field-Programmable Devices and Advanced CAD Tools", 33rd Design Automation Conf., Las Vegas, Nevada, June 1996.

18. Z. Zilic and Z.G. Vranesic, "New Interpolation Algorithms for Multiple-Valued Reed-Muller Forms", 26th Int. Symp. on Multiple-valued Logic, (IEEE), Santiago de Compostela, Spain, May 1996, pp. 16-23.

19. Z. Zilic and Z.G. Vranesic, "Using BDDs to Design ULMs for FPGAs", Proc. FPGA '96 - Int. Symp. on Field Programmable Gate Arrays, (ACM/SIGDA), Monterey, CA., pp. 24-30, Feb. 1996.

20. M. Jaseemuddin and Z.G. Vranesic, "Bidirectional Ring: An Alternative to the Hierarchy of Unidirectional Rings", Proc. Euro-Par '95 - Int. Conf. on Parallel Processing, Stockholm, Sweden, Aug. 1995, pp.567-578.

21. Z. Zilic and Z.G. Vranesic, "Reed-Muller Transform for Incompletely Specified Functions via Sparse Polynomial Interpolation", Proc. 25th Int. Symp. on Multiple-valued Logic, (IEEE), Bloomington, Indiana, May 1995.

22. S.J.E. Wilton, J. Rose and Z.G. Vranesic, "Architecture of Centralized Field-Configurable Memory", Proc. FPGA '95 - ACM Third Int. Symp. on Field Programmable Gate Arrays, Monterey, Ca., Feb. 1995, pp. 97-103.

23. S. Srbljic, Z.G. Vranesic and L. Budin, "Performance Prediction for Different Consistency Schemes in Distributed Shared Memory Systems", Third Int. Symp. on High-Performance Distributed Computing, (IEEE), San Francisco, Ca., Aug. 1994, pp. 296-302.

24. A.S. Kaviani and Z.G. Vranesic, "On Scheduling in Multiprocessor Systems Using Fuzzy Logic", Proc. 24th Int. Symp. on Multiple-valued Logic, (IEEE), Boston, Mas., May 1994, pp. 141-148.

25. M. Khellah, S. Brown and Z.G. Vranesic, "Minimizing Interconnection Delays in Array-Based FPGAs", Proc. Custom Integrated Circuits Conf., San Diego, Ca., May 1994, pp. 181-184.

26. S.J.E. Wilton and Z.G. Vranesic, "Architectural Support for Block Transfers in a Shared-Memory Multiprocessor", Proc. 5th IEEE Symp. on Parallel and Distributed Processing, Dallas, Texas, Dec. 1993, pp. 51-54.

27. M. Khellah, S. Brown and Z. Vranesic, "Modelling Routing Delays in SRAM-based FPGAs", Proc. CCVLSI'93, Banff, Alberta, Nov. 1993, pp. 6B.13-6B.18.

28. Z. Zilic and Z.G. Vranesic, "Multiple-Valued Logic in FPGAs", Proc. 36th Midwest Symp. on Circuits and Systems, Detroit, Mi., Aug. 1993.

29. Z.G. Vranesic, "Ring-Based Multiprocessors", Proc. Information Technology Interfaces 1993, Pula, Croatia, June 1993, pp. 25-30.

30. M. van de Panne, E. Fiume and Z.G. Vranesic, "Optimal Controller Synthesis Using Approximating-Graph Dynamic Programming", Proc. 1993 American Control Conf., San Francisco, Ca., June 1993, pp. 2322-2326.

31. Z. Zilic and Z. Vranesic, "Current-mode CMOS Galois Field Circuits", Proc. 23rd Int. Symp. on Multiple-valued Logic, (IEEE), Sacramento, Ca., May 1993,

32. M. Stumm, Z.G. Vranesic, K. Farkas and R. Unrau, "Experiences with the Hector Multiprocessor", Seventh Int. Parallel Proc. Symp. (Parallel Systems Fair), (IEEE), Newport Beach, Ca., April 1993, pp. 10-17.

33. M. van de Panne, E. Fiume and Z.G. Vranesic, "A Controller for the Dynamic Walk of a Biped Across Variable Terrain", Proc. 31st IEEE Conf. on Decision and Control, Tucson, Arizona, Dec. 1992, pp. 2668-2673.

34. M. van de Panne, E. Fiume and Z.G. Vranesic, "Control Techniques for Physically-Based Animation", Proc. Third Eurographics Workshop on Animation and Simulation, Cambridge, England, Sept. 1992, 15 pages.

35. K. Farkas, Z.G. Vranesic and M. Stumm, "Cache Consistency in Hierarchical-Ring-Based Multiprocessors", Proc. Supercomputing 92 (IEEE), Minneapolis, Mn., Nov. 1992, pp. 348-357.

36. K.S. Lei and Z.G. Vranesic, "Towards the Realization of 4-Valued CMOS Circuits", Proc. 22st Int. Symp. on Multiple-valued Logic, (IEEE), Sendai, Japan, May 1992.

37. R.J. Francis, J.S. Rose and Z.G. Vranesic, "Technology Mapping Lookup Table-Based FPGAs for Performance", Proc. 1991 Int. Conf. on CAD, (IEEE), Santa Clara, Ca., Nov. 1991, pp. 568-571.

38. R.J. Francis, J.S. Rose and Z.G. Vranesic, "Chortle-crf: Fast Technology Mapping for Lookup Table-Based FPGAs", Proc. 28th Design Automation Conf., (IEEE), Boulder, Co., June 1991, pp. 227-233.

39. C.P. Chong, K.C. Smith and Z.G. Vranesic, "On Improving the Linearity of DACs using TIAMPs", Proc. 1991 Int. Symp. on Circuits and Systems, (IEEE), Singapore, June 1991, pp. 1513-1516.

40. K.S. Lei and Z.G. Vranesic, "On the Synthesis of 4-valued Current Mode CMOS Functions", Proc. 21st Int. Symp. on Multiple-valued Logic, (IEEE), Victoria, B.C., May 1991, pp. 147-155.

41. Z.G. Vranesic, V.C. Hamacher, A.K. Sanwalka and S.G. Zaky, "A Hybrid Token/Insertion Ring LAN", Proc. INFOCOM'91, (IEEE), Miami, Fl., Apr. 1991, pp. 211-220.

42. Z.G. Vranesic, M. Stumm, D.M. Lewis and R. White, "Hector - A Hierarchically Structured Shared Memory Multiprocessor", Proc. 24th Hawaii Int. Conf. on System Sciences, (IEEE), Kauai, Ha., Jan. 1991, pp. 444-453.

43. S.D. Brown, J.S. Rose and Z.G. Vranesic, "A Detailed Router for Field-Programmable Gate Arrays", IEEE Int. Conf. on Computer-Aided Design, Santa Clara, Ca., Nov. 1990, pp. 382-385. (distinguished paper designation).

44. L.K. Chan and Z.G. Vranesic, "TORMLAN - A Multichannel Local Area Network Protocol", Proc. INFOCOM'90, (IEEE), San Francisco, Ca., May 1990, pp. 756-765.

45. S.G. Zaky, Z.G. Vranesic and M.H. Abd-El-Barr, "Step-wise Synthesis of CCD MVL Functions", Proc. 20th Int. Symp. on Multiple-valued Logic, (IEEE), Charlotte, NC., May 1990, pp. 300-307.

46. C.P. Chong, K.C. Smith and Z.G. Vranesic, "Three-input Amplifiers", Proc. 1990 Int. Symp. on Circuits and Systems, (IEEE), New Orleans, La., May 1990, pp. 3217-3220.