- V. Manohararajah, S.D. Brown and Z.G. Vranesic,
"Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping",
IEEE Trans. on CAD of ICs and Systems, Vol. 25, No. 11,
Nov.. 2006, pp. 2331-2340.
- D. Debnath and Z.G. Vranesic, "A Fast Algorithm for OR-AND-OR Synthesis",
IEEE Trans. on CAD of ICs and Systems, Vol. 22, No. 9, Sept. 2003,
pp. 1166-1176.
- A.G. Kirk, D.V. Plant, T.H. Szymanski, Z.G. Vranesic, F.A.P. Tooley,
D.R. Rolston, M.H. Ayliffe, F.K. Lacroix, B. Robertson, E. Bernier
and D.F. Brosseau,
"Design and Implementation of a Modulator-Based Free-Space Optical
Backplane for Multiprocessor Applications",
Applied Optics, Vol. 42, Issue 14, 2003, pp. 2465-2481.
- Z. Zilic and Z.G. Vranesic, "A Deterministic Multivariate Interpolation
Algorithm for Small Finite Fields", IEEE Trans. on Computers, Vol. 51,
No. 9, Sept.2002, pp. 1100-1105.
- S. Wilton, J. Rose and Z.G. Vranesic,
"Structural Analysis and Generation of Synthetic Digital Circuits
with Memory", IEEE Trans. on VLSI Systems, Vol. 9, No. 1, 2001, pp. 223-226.
- K.I. Farkas, P. Chow, N.P. Jouppi and Z.G. Vranesic, "The
Multicluster Architecture: Reducing Cycle Time Through Partitioning",
Int. Journal of Parallel Programming, Vol. 27, No. 5, 1999, pp. 327-356.
- S. Wilton, J. Rose and Z. Vranesic, "The Memory/Logic Interface
in FPGAs with Large Embedded Memory Arrays", IEEE Trans. on VLSI Vol. 7,
No. 1, Mar 1999, pp. 80-91.
- Z. Zilic and Z.G. Vranesic, "Using Decision Diagrams to Design
ULMs for FPGAs", IEEE Trans. on Computers, Vol. 47, No. 9, Sept. 1998,
pp. 971-982.
- S. Srbljic, Z.G. Vranesic, M. Stumm and L. Budin, "Analytical
Prediction of Performance for Cache Coherence Protocols".
IEEE Trans. on Computers, Vol. 46, No. 11, Nov. 1997, pp. 1155-1173.
- S.D. Brown, M. Khellah and Z.G. Vranesic, "Minimizing
FPGA Interconnect Delays", IEEE Design and Test of Computers,
Vol. 13, No. 4, 1996, pp. 16-23.
- Z. Zilic and Z.G. Vranesic, "Polynomial Interpolation
for Reed-Muller Forms for Incompletely Specified Functions",
Journal of Multiple-Valued Logic, Vol. 1, No. 1, Oct. 1996, pp.
1-27.
- Z. Zilic and Z.G. Vranesic, "A Multiple-Valued Reed-Muller
Transform for Incompletely Specified Functions", IEEE Trans.
on Computers, Vol. 44, No. 8, Aug. 1995, pp. 1012-1020.
- K. Farkas, Z. Vranesic and M. Stumm, "Scalable Cache
Consistency for Hierarchically-Structured Multiprocessors",
Journal of Supercomputing Vol 8, No.4, 1995, pp. 345-369.
- S.D. Brown, J.S. Rose and Z.G. Vranesic, "A Stochastic
Model to Predict the Routability of Field-Programmable Gate Arrays",
IEEE Trans. on CAD of ICs and Systems, Vol. 12, No. 12, Dec. 1993,
pp. 1827-1838.
- Z.G. Vranesic, "Ring-Based Multiprocessors", Journal
of Computing and Information Technology, CIT-1/3, Dec. 1993, pp.
165-172.
- M. van de Panne, E. Fiume and Z.G. Vranesic, "Physically
Based Modeling and Control of Turning", Computer Vision,
Graphics, and Image Processing: Graphical Models and Image Processing,
Vol. 55, No. 6, Nov. 1993, pp. 507-521.
- S.D. Brown, J.S. Rose and Z.G. Vranesic, "A Detailed
Router for Field-Programmable Gate Arrays", IEEE Trans. on
CAD of Circuits and Systems, Vol. 11, No. 5, May 1992, pp. 620-628.
- M.H. Abd-El-Barr, Z.G. Vranesic and S.G. Zaky, "Algorithmic
Synthesis of MVL Functions for CCD Implementation", IEEE
Trans. on Computers, Vol. 40, No. 8, Aug 1991, pp. 977-986.
- Z.G. Vranesic, M. Stumm, D.M. Lewis and R. White, "Hector
- A Hierarchically Structured Shared Memory Multiprocessor".
IEEE Computer, Vol. 24, No. 1, Jan. 1991, pp. 72-79.
- S.D. Brown and Z.G. Vranesic, "A chip for fault-detection
experiments", Journal of Semicustom ICs, Vol. 8, Sept. 1990,
pp. 48-50.
- M. van de Panne, E. Fiume and Z.G. Vranesic, "Reusable
Motion Synthesis Using State-Space Controllers", Computer
Graphics, Vol. 24, No. 4, Aug. 1990, pp. 225-234.
- M.H. Abd-El-Barr and Z.G. Vranesic, "Cost Reduction in
the CCD Realization of MVMT Functions", IEEE Trans. on Computers,
Vol. 39, No. 5, May 1990, pp. 702-706.