A Bursty Multi-Port Memory Controller with QoS Guarantee

Zefu Dai

University of Toronto

November, 2011

Embedded multimedia system-on-chips place an increasing demand on
multiport memory controllers (MPMCs) for higher memory system
performance and energy efficiency, in addition to satisfying various
types of quality-of-service requirements, such as minimum latency and
bandwidth guarantees.  While previous works have attempted to solve
different aspects of the MPMC design challenges, none has succeeded in
addressing all these problems simultaneously. In this paper, we
propose a new approach that can provide, not only minimum latency and
bandwidth guarantees, but also higher efficiency in utilization of
physical DRAM bandwidth and dynamic bandwidth made available by
underutilized ports. Experimental resutls show that, on typical
multimedia workloads, our approach improves the effective DRAM
bandwidth and energy efficiency by as much as 1.9x and 1.49x,
respectively. In addition, the response latency for latency-sensitive
port is improved by more than 6X, while preserving bandwidth guarantee
for all ports.