Bill Teng and Jason Anderson
University of Toronto
May, 2011
We explore using pulsed latches for timing optimization -- a first in the FPGA community. Pulsed latches are transparent latches driven by a clock with a non-standard (non-50%) duty cycle. We exploit existing functionality within commercial FPGA chips to implement latch-based optimizations that do not have the power or area drawbacks associated with other timing optimization approaches, such as clock skew and retiming. We propose an algorithm that iteratively replaces certain flip-flops in a logic design with latches for an improvement in circuit speed. Results show that the majority of the performance improvement achieved by using multiple skewed clocks can also be achieved using a single clock and latches. We also consider the impact of short delay paths (i.e. min delays), which can cause hold-time violations. When short path delays are set to be 70% of long path delays, our latch-based optimization, operating on the routed design, provides a 5% performance improvement, on average, essentially for 'free' (i.e. without any re-routing/delay padding). We show that short paths greatly hinder the ability of using latches for speed improvement, motivating further work to reduce their effects.