Partial Reconfiguration on Altera's Devices - Hardware Support & Software Flow

Slide Link

Mark Bourgeault

Altera Toronto

June, 2011

Partial reconfiguration is the process of configuring a portion of a field-programmable gate array while the other part is still running/operating.  This capability enables certain applications to be implemented with lower area and lower power by optimizing the contents of the FPGA fabric over the time-domain.  Altera's 28nm device families (Stratix V, Arria V, and Cyclone V) represent the first product offering (by Altera) with support for partial reconfiguration. In this talk, I will provide an overview of the hardware capabilities and the Quartus software flow that Altera will be releasing shortly, which will enable users to build large systems that effectively utilize partial reconfiguration in Altera's 28nm device families.