NetTM: Faster and Easier Synchronization For Soft MultiCores Via Transactional Memory

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Martin Labrecque and Greg Steffan

University of Toronto

March, 2011

As reconfigurable computing hardware and in particular FPGA-based systems-on-chip comprise an increasing number of processor and accelerator cores, supporting sharing and synchronization in a way that is scalable and easy to program becomes a challenge.  Transactional memory (TM) is a potential solution to this problem, and an FPGA-based system provides the opportunity to support TM in hardware (HTM).  Although there are many proposed approaches to support HTM for ASIC multicores, these do not necessarily map well to FPGA-based soft multicores. In this presentation, we will describe NetTM: support for HTM in an FPGA-based soft multithreaded multicore that matches the strengths of FPGAs---in particular by careful selection of TM features such as version and contention management, and with conflict detection via support for application-specific signatures.  We evaluate our system using the NetFPGA platform and four network packet processing applications that are threaded and shared-memory. Relative to NetThreads, an existing two-processor four-way-multithreaded system with conventional lock-based synchronization, we find that adding HTM support (i) maintains a reasonable operating frequency of 125MHz with an area overhead of 20\%, (ii) can ``transactionally'' execute lock-based critical sections with no software modification, and (iii) achieves 6%, 54% and 57% increases in packet throughput for three of four packet processing applications studied, due to reduced false synchronization.