Using Partial Reconfiguration in An Embedded Messahe-Passing System

Slide Link

Manuel Saldana, Hao Jun Liu, Arun Patel and Paul Chow

ArchES Computing and the University of Toronto

March, 2011

Partial Reconfiguration (PR) is an FPGA feature that allows the  modification of certain parts of an FPGA while the rest of it continues to operate without disruption. This distinctive characteristic of FPGAs has many potential benefits but also challenges.  The lack of good CAD tools and the deep hardware knowledge requirement result in a hard to use feature.  In this talk, the new Partition-based Xilinx PR flow is  used to incorporate PR within a MPI-based message-passing framework to  allow hardware designers to create template bitstreams, which are  pre-designed, pre-routed, generic bitstreams that other users can reuse for different applications. The goal is to provide a simplified, reusable, high-level and portable PR interface for X86-FPGA hybrid machines. PR issues such as local reset of reconfigurable modules and context saving and restoring are addressed in this paper followed by preliminary PR overhead measurements and examples.