Impact of FPGA Architecture on Resource Sharing in High-Level

Stefan Hadjis

University of Toronto

January, 2012

Resource sharing is a key area-reduction approach in high-level
synthesis (HLS) in which a single hardware functional unit is used to
implement multiple operations in the high-level circuit specification.
We show that the utility of sharing depends on the underlying FPGA
logic element architecture and that different sharing trade-offs exist
when 4-LUTs vs. 6-LUTs are used. We further show that certain
multi-operator patterns occur multiple times in programs, creating
additional opportunities for sharing larger composite functional units
comprised of patterns of interconnected operators.  A sharing
cost/benefit analysis is used to inform decisions made in the binding
phase of an HLS tool, whose RTL output is targeted to Altera
commercial FPGA families: Stratix IV (dual-output 6-LUTs) and Cyclone
II (4-LUTs).