Multi-Ported Memories for FPGAs via XOR

Gregory Steffan

University of Toronto

February, 2012

Multi-ported memories are challenging to implement with FPGAs since the block
RAMs included in the fabric typically have only two ports. Any design that
requires a memory with more than two ports must therefore be built out of logic
elements or by combining multiple block RAMs. Our recently-proposed Live Value
Table (LVT) design provides a significant operating frequency improvement over
conventional approaches (FPGA'10).  In this work (to appear in FPGA'12) we
present an alternative approach based on the XOR operation that provides
multi-ported memories that use far less logic but more block RAMs than LVT
designs, and are often smaller and faster for memories that are more than 512
entries deep.  We show that (i) both designs can exploit multipumping to trade
speed for area savings, (ii) that multi-pumped XOR designs are significantly
smaller but moderately slower than their LVT counterparts, and (iii) that both
the LVT and XOR approaches are valuable and useful in different situations,
depending on the constraints and resource utilization of the enclosing design.

NOTE: A preliminary version of this work was presented at an FPGA seminar in
May'11; since then we have improved the designs of both LVT and XOR, made them
compatible/comparable in their read/write timing, and have a whole new set of