On the Difficulty of Pin-to-Wire Routing in FPGAs

Niyati Shah and Jonathan Rose

University of Toronto

June, 2012

While FPGA programmable routing networks are designed to connect logic
block output pins to input pins, FPGA users and architects sometimes
become motivated to create connections between pins and specificwires
in an FPGA. We call these *pin-to-wire* connections, and they are
motivated by several reasons: first, a desire to employ
routing-by-abutment, as commonly done in custom VLSI, to build
modular, pre-laid out systems. Second, partial reconfiguration of
FPGAs often requires that circuits in the FPGA connect by abutment.
Third, pin-to-wire routing is required to make use of resources that
reside within the routing network itself, such as the plentiful
multiplexers in the network, or even the configuration bits
themselves. In this work we attempt to understand and measure how
difficult it is to form such pin-to-wire connections. We show, for
example, under an experimental scenario close to routing-by-abutment,
that the total routed wirelength compared to a flat placement of the
complete system increases by about 6%, that the critical path delay
increases by 15% and the router effort goes up by a factor of three.
To achieve this result, it is important to be careful in selecting the
specific target wires.  Overall we demonstrate that while pin-to-wire
connections definitely impose increased stress on the routing
architecture and router, it is possible to route some reasonable
number of them, and so they can be used under some circumstances.