Brad Hutchings
Brigham Young University
May, 2012
The impact of FPGA physical CAD research (placement and routing algorithms, etc.) is limited when experiments cannot be conducted and verified with actual devices. The details of FPGA micro-architecture (routing architecture, CLB and LAB structure, etc.) closely interact with backend CADand significantly impact the final results of backend CAD experiments. Indeed some interesting experiments are simply not feasible without ready access to the details of the micro-architecture of actual FPGA devices and without access to their related flows. HMFlow is an example of a experiment that was enabled by access to the detailed FPGA micro-architecture of Xilinx FPGAs via XDL. HMFlow is an experimental flow that attacks the time-consuming task of FPGA implementation (synthesis, map, place and route) by preserving and reusing previous computational effort in the form of pre-compiled hard macros. Large FPGA systems are broken down into relocatable modules that are stored in fully compiled form in a library. These modules are compiled once and then are reused by relocating the module onto the device and connecting its ports to other module ports and/or IO pads. Although hard macros are compiled usingXilinx CAD flows, the relocation, placement and routing -- inter-hard-macro -- is performed using specialized placers and routers that were developed specifically for HMFlow. These placers and routers are aware of all micro-architectural details and can implement large working designs that have been tested via download.
Preliminary results from HMFlow are quite promising; designs implemented with HMFlow with a pre-compiled hard-macro library can be compiled 10X-50X faster than conventional place and route and achieve clock rates that are up to 80% of those provided by conventional flows. HMFlow is based on RapidSmith, a tool-development suite that extracts Xilinx architectural details into a form that is useful for the development of placement, routing and other physical design tools. RapidSmith was feasible because of access provided by Xilinx via XDL, an interface that completely describes the entire physical structure of Xilinx FPGA devices.