Kevin E. Murray
University of Toronto
Oct, 2013
Benchmarks play a key role in FPGA architecture and CAD research,
enabling the quantitative comparison of tools and architectures. It is
important that these benchmarks reflect modern designs which are large
scale systems that make use of heterogeneous resources; however, most
current FPGA benchmarks are both small and simple. In this paper we
present Titan, a hybrid CAD flow that addresses these issues. The flow
uses Altera's Quartus II FPGA CAD software to perform HDL synthesis
and a conversion tool to translate the result into the academic BLIF
format. Using this flow we created the Titan23 benchmark set, which
consists of 23 large (90K-1.8M block) benchmark circuits covering a
wide range of application domains. Using the Titan23 benchmarks and a
detailed model of Altera's Stratix IV architecture we compared the
performance and quality of VPR and Quartus II targeting the same
architecture. We found that VPR is at least 2.7x slower, uses 5.1x
more memory and 2.6x more wire compared to Quartus II. Finally, we
identified that VPR's focus on achieving a dense packing is
responsible for a large portion of the wire length gap.