URISC: Ultra-reduced Instruction-set Co-processors 2

Hiren Patel

University of Waterloo

March 2014

This work presents a method to reliably perform computations in the presence of permanent faults arising from aggressive technology scaling. Our method is based on the observation that a single Turing-complete instruction can mirror the semantics of any other instruction. One such instruction is the subleq instruction, which has been used for instructional purposes in the past. The scope of using such an instruction is far greater than that of instructional purposes, and thus, we present its applicability to fault tolerance. In particular, we extend a MIPS processor with a co-processor (called the ultra-reduced instruction set co-processor – URISC) that implements the subleq instruction. We use the URISC to execute sequences of subleq to mimic the semantics of instructions that are known to be faulty on the MIPS core after testing. Our LLVM compiler back-end generates the sequence of subleq for instructions marked as faulty. We also use the URISC to present a method for fault detection at the microarchitecture/instruction level. Instructions in the code are selected for redundant execution on the URISC based on a check window criterion that enables designers to trade-off fault detection latency and likelihood with execution time. In addition, URISC instruction-set extensions and loop unrolling are proposed as two techniques to further reduce the performance overhead of fault detection.

Speaker Bio:

Hiren Patel is an assistant professor in the Electrical and Computer Engineering department at the University of Waterloo, Canada. His research interests are in embedded systems covering both software and hardware aspects. This includes models of computation, real-time embedded systems, computer architecture, and system-level design.