Extended Static Timing Analysis

This work introduces Extended Static Timing Analysis (ESTA), a method for analyzing the timing behaviour of a digital circuit while considering the impact of the circuit logic on its timing behaviour. Unlike conventional STA, which produces single delay values by assuming worst-case switching, ESTA produces a path-delay distribution (i.e. a set of delays and thier probabilities) accross all possible input combinations.

This type of analysis has applications to approximate computing, as it enables a more nuanced analysis of circuits operating beyond thier 'safe' operating frequency, allowing us to quantify of how often errors will occur.

For more details see our TCAD and DATE papers.

TCAD 2018 Paper

K. E. Murray, A. Suardi, V. Betz, G. Constantinides, "Calculated Risks: Quantifying Timing Error Probability with Extended Static Timing Analysis", To appear in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2018, (pdf, DOI: 10.1109/TCAD.2018.2821563)

DATE 2017 Paper

K. E. Murray, A. Suardi, V. Betz, G. Constantinides, "Quantifying Error: Extending Static Timing Analysis with Probabilistic Transitions", Design, Automation & Test in Europe (DATE), 2017, pp. 1486-1491 (pdf, DOI: 10.23919/DATE.2017.7927226)


Benchmark Source Files

esta_DATE2017_benchmarks.tar.gz (15MB):

Monte Carlo Generated Max-Delay Histograms

esta_DATE2017_mc_histograms.tar.gz (278KB):