Titan aims to address two issues. First, the extremly small size of benchmarks used in most academic FPGA research. Second, the difficulty of converting real world FPGA designs into formats academic tools can understand. Titan addresses both of these issues by providing the Titan23 benchmark suite and the Titan flow.
The Titan23 benchmark suite is a collection of large FPGA benchmark circuits suitable for evaluating new FPGA architectures and CAD tools. These designs are considerably larger than those found in many other FPGA benchmark suites, and make extensive use of heterogeneous resources such as DSP and RAM blocks.
The Titan flow allows FPGA benchmark circuits described in HDL to be used in academic CAD tools after being synthesized using Altera's Quartus II. The translation from Altera's VQM file format to the academic BLIF is performed by our vqm2blif tool.
For more details on the Titan23 benchmarks and the Titan flow please see our TRETS and FPL2013 papers.
K. E. Murray, S. Whitty, S. Liu, J. Luu and V. Betz, "Timing-Driven Titan: Enabling Large Benchmarks and Exploring the Gap Between Academic and Commercial CAD", ACM Trans. Reconfig. Technol. Syst., April 2015, pp. 10:1 - 10:18. (pdf)
K. E. Murray, S. Whitty, S. Liu, J. Luu and V. Betz, "Titan: Enabling Large and Complex Benchmarks in Academic CAD", IEEE Int. Conf. on Field-Programmable Logic and Applications, 2013, 1-8. (pdf)
A short tutorial was also accepted to FPL 2013 as a demo. It focuses on the details of the HDL to BLIF conversion process.
The Titan release includes:
The release file is in tar.gz format, it can be extracted on a linux command line as follows: tar -xzvf filename.tar.gz
Note that the extracted release can be quite large due to the benchmark netlists (~37GB).Current Release:
Version 1.2.0: April 6, 2017
Version 1.0.0: June 22, 2013
Version 0.9.0: May 29, 2013