Titan

Large and Complex Benchmarks in Academic CAD

Titan aims to address two issues. First, the extremly small size of benchmarks used in most academic FPGA research. Second, the difficulty of converting real world FPGA designs into formats academic tools can understand. Titan addresses both of these issues by providing the Titan23 benchmark suite and the Titan flow.

The Titan23 benchmark suite is a collection of large FPGA benchmark circuits suitable for evaluating new FPGA architectures and CAD tools. These designs are considerably larger than those found in many other FPGA benchmark suites, and make extensive use of heterogeneous resources such as DSP and RAM blocks.

The Titan flow allows FPGA benchmark circuits described in HDL to be used in academic CAD tools after being synthesized using Altera's Quartus II. The translation from Altera's VQM file format to the academic BLIF is performed by our vqm2blif tool.

For more details on the Titan23 benchmarks and the Titan flow please see our TRETS and FPL2013 papers.

TRETS Paper

K. E. Murray, S. Whitty, S. Liu, J. Luu and V. Betz, "Timing-Driven Titan: Enabling Large Benchmarks and Exploring the Gap Between Academic and Commercial CAD", ACM Trans. Reconfig. Technol. Syst., April 2015, pp. 10:1 - 10:18. (pdf)

FPL 2013 Paper

K. E. Murray, S. Whitty, S. Liu, J. Luu and V. Betz, "Titan: Enabling Large and Complex Benchmarks in Academic CAD", IEEE Int. Conf. on Field-Programmable Logic and Applications, 2013, 1-8. (pdf)

Tutorial/Demo

A short tutorial was also accepted to FPL 2013 as a demo. It focuses on the details of the HDL to BLIF conversion process.

Release

The Titan release includes:

• HDL for the Titan23 benchmarks
• VQM and BLIF netlists for the Titan23 benchmarks (targeting Altera's Stratix IV)
• VPR compatible architecture capture of Altera's Stratix IV device family
• The vqm2blif tool to convert from VQM to BLIF
• Scripts to run the Titan flow

The release file is in tar.gz format, it can be extracted on a linux command line as follows: tar -xzvf filename.tar.gz

Note that the extracted release can be quite large due to the benchmark netlists (~37GB).

Version 1.3.1: Nov 25, 2019

• Architecture file compatibility updates (e.g. 'tiles' tags)
• Added 'picosoc' and 'murax' benchmarks from symbiflow to 'other_benchmarks'
• NOTE: Compatible with VTR after revision 604115

Version 1.3.0: May 28, 2019

• Added improved routing switch block pattern to capture Stratix IV's hierarchical short/long wire connectivity
• Extend direct-connect links to include non-LAB blocks
• Convert all blocks to a 3-sided routing architecture
• Re-generate SDC files to ignore extremely small clocks (focus on main system clocks)
• Added minimum-delay timing model, and several enahncements to max-delay timing model
• Regenerated netlists with Quartus v18.0
• NOTE: Compatible with VTR 8 release

Version 1.2.0: April 6, 2017

• Added primitive internal timing for RAM and DSP blocks to stratixiv_arch.timing.xml
• Added missing pack-patterns for DSP blocks to stratixiv_arch.timing.xml
• Regenerated netlists with Quartus v16.1
• Updated vqm2blif to include multi-clock primitives
• NOTE: Compatible with VTR revision 02e5917 or later (not compatible with VTR 7.0 release)

Version 1.1.0: July 7, 2014

• Improved benchmark compatibility with VPR
• Enhanced architecture capture of Stratix IV
• Added timing model for Stratix IV
• Added equivalent VPR and Quartus II timing constraints
• Fix vqm2blif compatibility with GNU Bison 3.0
• NOTE: Requires VPR trunk r4292 or later (not compatible with VPR 7.0 release)

Version 1.0.0: June 22, 2013

• Shorten some benchmark names
• Improve documentation

Version 0.9.0: May 29, 2013

• Initial early access release