VQM to BLIF Convertor

Last Updated: August 23, 2011.


The VQM to BLIF convertor facilitates the use of Altera©'s Quartus® II software for high-level circuit elaboration in other hardware synthesis flows that accept BLIF as a standard circuit description language. This allows users to compare their placement and routing algorithms to a commercial tool, as well as use the Verilog, System Verilog and VHDL support of Quartus II to pass realistic circuits through their software.


Current open-source FPGA CAD software flows have high value in their ability to accept a general description of an FPGA Architecture. These flows are used to conduct experiments using standardized benchmark circuits on completely hypothetical FPGAs. However, current tools cannot support the full Verilog standard for hardware description, and thus these open-source tools are limited in their ability to process large circuits. By replacing these limited front-end tools with Quartus II, we gain the ability to feed the rest of the flow with large, realistic and relevant circuits that simply weren't compatible before.


The full release of VQM-to-BLIF V.1.0 can be downloaded here.


This poster summarizes the goals and results of this project, as of August 2011.


The researchers gratefully acknowledge the support and contributions of the following groups and individuals:

The VTR Project at the University of Toronto for an XML Parser and downstream testing.
Tomasz Czajkowski for a VQM Parser.
Daniele Paladino for early software development aid.
NSERC for providing funding through an Undergraduate Student Research Award.