FPGA Architecture Evaluation and Technology Mapping using Boolean Satisfiability
Abstract
This paper presents a technology mapping algorithm that can be used to
evaluate the robustness of any FPGA programmable logic block (PLB). This
algorithm, named SATMAP , uses Boolean satisfiability (SAT) to determine
if a logic cone can be implemented in a given PLB. This algorithm is
a fundamental tool needed to study the utility of any proposed FPGA
logic block. Our approach is the first tool of its kind that allows
radical new features of FPGA logic blocks to be evaluated in a rigorous
scientific way.
Reference
Andrew C. Ling, Deshanand P. Singh, Valavan Manohararajah, and Stephen D. Brown, "FPGA Architecture Evaluation and Technology Mapping using Boolean Satisfiability", in Proceedings of the International Workshop on Logic and Synthesis, Lake Arrowhead, CA, June 2005, pp. 399-406.
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