Our Seminars from 2014
- Massively Parallel Placement
- High-Level Synthesis with Bluespec: An FPGA Designer's Perspective
- Addressing societal concerns in active seti
- URISC: Ultra-reduced Instruction-set Co-processors 2
- Speeding Up FPGA Placement: Parallel Algorithms and Methods
- The Case for Embedded Networks-on-Chip on FPGAs
- The Three Ages of FPGA