6.0 Approaches for Module Generators

M. Buric, "Design of Module Generators and Silicon Compilers", in Design systems for VLSI Circuits: Logic Synthesis and Silicon Compilation, G. De Micheli, A. Sangiovanni-Vincentelli and P. Antognetti, Eds., Martinus Nijhoff Publishers, pp. 403-438, 1987.

2. R. Lipton et al, "ALI: A Procedural Language to Describe VLSI Layouts", Proc, 19th ACM/IEEE Design Automation Conf., 1982.

3. R. Mayo and J. Ousterhout, "Pictures with parentheses: combining graphics and procedures in a VLSI layout tool," Proc. 20th Design Automation Conf., June 1983.

4. D. Eddington et al., "CMOS Cell Compilers for Custom IC Design", Proc. Custom IC Conf., pp. 512-517, 1984.

5. R. Mayo, "Mocha Chip: A System for the Graphical Design of VLSI Module Generators," Proc. IEEE Int'l Conf. on CAD, pp. 74-77, Nov. 1986.

7.0 Logic Optimization

R. Brayton "Algorithms for Multi-Level Logic Synthesis and Optimization," in Design systems for VLSI Circuits: Logic Synthesis and Silicon Compilation, G. De Micheli, A. Sangiovanni-Vincentelli and P. Antognetti, Eds., Martinus Nijhoff Publishers, pp. 197-248, 1987. or (shorter, but harder to read): R. Brayton, R. Rudell, A. Sangiovanni-Vincentelli, A. Wang, "MIS: A Multiple-Level Logic Optimization System," IEEE Trans. Computer-Aided Design, Vol. CAD-6 No. 6, November 1986, pp. 1062-1081.

2. R.E. Bryant, "Graph-Based Algorithms for Boolean Function Manipulation," IEEE Trans. on Computers, Vol. C-35 No. 8, August 1986, pp. 677-691.

3. R.K. Brayton, et. al. Logic Minimization Algorithm for VLSI Synthesis, Kluwer Academic Publishers, Boston, 1984.

4. K.A. Bartlett, et. al "Multilevel Logic Minimization Using Implicit Don't Cares," IEEE Trans. Computer-Aided Design, Vol. CAD-7 No. 6, June 1988, pp. 723-740.

5. K. Bartlett et. al, "Synthesis and Logic Optimization under Timing Constraints," IEEE Trans. Computer-Aided Design, Vol. CAD-5 No. 4, October 1986, pp. 582-596.

6. D.E. Wallace, M.S. Chandrasekhar, "High-Level Delay Estimation for Technology-Independent Logic Equations," Proc. 1990 International Conference on Computer-Aided Design (ICCAD), pp. 188-191, November 1990.

7. A. Shen, A. Ghosh, S. Devadas, K. Keutzer, "On Average Power Dissipation and Random Patter Testability of CMOS Combinational Logic Networks," Proc. ICCAD '92, pp. 402-407.

8. D. Brand, A. Drumm, SKundu, P.Narain, "Incremental Synthesis," Proc. ICCAD '94, pp. 14-17.

9. S. Iman, M. Pedram, "Multi-Level Network Optimization for Low Power," Proc. ICCAD '94, pp. 372-377.

8.0 Technology Mapping

K. Keutzer, ''DAGON: Technology Binding and Local Optimization by DAG Matching,'' Proc. 24th Design Automation Conference, June 1987, pp. 341-347.

2. E.Detjens et. al, ''Technology Mapping in MIS'', Proc. ICCAD 87, Nov 1987, pp. 116-119.

3. R.J Francis, J. Rose, Z. Vranesic, "Chortle-crf: Fast Technology Mapping for Lookup Table-Based FPGAs," 28th ACM/IEEE Design Automation Conference, June 1991, pp. 227-233.

4. R. Lisanke, F. Brglez, G. Kedem, ''McMAP: A Fast Technology Mapping Procedure for Multi-Level Logic Synthesis,'' Proc. ICCD, pp. 252-256, October 1988.

9.0 Synchronous Logic Synthesis

S. Devadas et. al., "MUSTANG: State Assignment of Finite State Machines Targeting Multilevel Lobic Implementations," IEEE Trans. Computer-Aided Design, Vol. CAD-7, No.12, December 1988, pp. 1290-1300.

2. G. DeMicheli, "Synthesis of Control Systems," in Design systems for VLSI Circuits: Logic Synthesis and Silicon Compilation, G. De Micheli, A. Sangiovanni-Vincentelli and P. Antognetti, Eds., Martinus Nijhoff Publishers, pp. 327-364, 1987.

3. Try all of IEEE Trans. Computer-Aided Design, Vol CAD-10, No. 1, January 1991, including the following two:.

4. K. Bartlett, G. Borriello, S. Raju, "Timing Optimization of Multiphase Sequential Logic", IEEE Trans. Computer-Aided Design, Vol CAD-10, No. 1, January 1991, pp. 51-62.

5. S. Malik et. al, "Retiming and Resynthesis: Optimizing Sequential Networks with Combinational Techniques," IEEE Trans. Computer-Aided Design, Vol CAD-10, No. 1, January 1991, pp. 74-84.

6. N. SHenoy, R. Rudell, "Efficient Implementation of Re-timing", Proc. ICCAD '94, pp. 226-233.

7. J. Grodstein et. al, "Optimal Latch Mapping and Retiming Within a Tree," Proc. ICCAD '94, pp. 242-246.

10.0 High-Level Synthesis

M. McFarland, A. Parker, R. Camposano, "Tutorial on High-Level Synthesis," Proc. 25th ACM/IEEE Design Automation Conference, pp. 330-336, 1988. (contains many references).

2. C-J. Tseng, D.P. Siewiorek, "Automated Synthesis of Data Paths in Digital Systems," IEEE Trans. Computer-Aided Design, Vol. CAD-5, No.3, July 1986, pp. 379-395.

3. P.G. Paulin, J.P. Knight, "Force-Directed Scheduling for the Behavioral Synthesis of ASICs," IEEE Trans. Computer-Aided Design, Vol. CAD-8 No. 6, June 1989, pp. 661-679.

4. P.G. Paulin, J.P. Knight, "Scheduling and Binding Algorithms for High-Level Synthesis" Proc. 26th ACM/IEEE Design Automation Conference, 1989, pp. 1-6.

5. G. DeMicheli, D. Ku, "HERCULES - A System for High-Level Synthesis," Proc. 25th ACM/IEEE Design Automation Conference, 1988, pp. 483-488.

6. H. Trickey, "Flamel: A High Level Hardware Compiler," IEEE Trans. Computer-Aided Design, Vol. CAD-6 No. 2, March 1987, pp. 259-269.

7. T.J. Kowalski, D.E. Thomas, "The VLSI Design Automation Assistant: What's in a Knowledge Base," Proc. 22nd ACM/IEEE Design Automation Conference, 1985, pp. 252-258.

8. For High-Level Synthesis, see also the special issue of IEEE, Design & Test, Vol 7, No. 5, October 1990.