ECE241F Lab 3
You are to create two of logic circuits to drive one of the seven-segment displays on the Altera UP-1 board. Please see Section 5.0 for details of how to use and hook up to these boards. (In particular, note that to turn a segment on, you must drive the corresponding pin to a logical "0").
Your preparation, to be marked, should consist of the VHDL code and the simulator output for all circuits. Print out the simulation results and VHDL code for marking. Use the timing simulator for the 7128 device if you're using the student version of maxplus2.
X3 X2 X1X0 | Display (note the capitalization) |
---|---|
0000 | 0 |
0001 | 1 |
0010 | 2 |
0011 | 3 |
0100 | 4 |
0101 | 5 |
0110 | 6 |
0111 | 7 |
1000 | 8 |
1001 | 9 |
1010 | A |
1011 | b |
1100 | C |
1101 | d |
1110 | E |
1111 | F |
Determine the equations for the 7-segment display segments, and minimize them using the Karnaugh-map method described in class. Write VHDL code to represent the logic function for each segment as a boolean equation (with AND, NOT, OR etc.). Simulate and test your equations using the maxplus2 functional or timing simulation on the MAX 7128S device.
Fairness alert: if your last name is longer than 8 unique letters, you need only do 8 unique characters of it. If your last name is shorter than 8 characters, you must add more letters of your first name until you have coded at least 8 unique characters.
Since you will only need to do 8 codes, you can leverage the don't cares that will be available in the truth tables.