As part of the GILES
project, we created an entire FPGA that
was taped out March 24, 2004.
The following table summarizes the architectural parameters of the FPGA we created.
| Parameter |
Value |
| LUT Size, k |
4 |
| Cluster Size, N |
3 |
| Number of Cluster Inputs, I |
8 |
| Number of Tracks Per Channel |
20 |
| Track Length |
4 |
| % Buffered Tracks |
100 |
| Fc, input |
0.600 |
| Fc, output |
0.333 |
| Fc, pad |
0.600 |
| Array Size, nx x ny |
8 x 8 |
| Total Number of LUTs |
192 |
| Total Number of I/O's |
64 |
The design was implemented in a 0.18 um 6-metal layer CMOS process
from TSMC. There are 358,374 transistors in the design which
occupied a silicon area of 2.4 mm by 2.4 mm. Click here to see a
picture of the final layout.
Click here to download a spice netlist
of the entire design. Unfortunately, to satisfy our non-disclosure
agreements, we have had to remove the netlists for the standard cells
and the pad cells we used in our design. To use the entire
design, you will have to substitute in your own definition for the
cells. These cells are only used for the programmer. The
complete circuit for the logic tiles is included in the netlist.
If you would like the netlist in an alternate form, e-mail ikuon at the
previously mentioned address since we may be able to help.
Click here for a report on the testing of the chip received in November, 2004.
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