As described in Section 2, the effective data width of
each array can be set by configuring the L1 data mapping blocks. In the
previous section, it was assumed that the set of effective output widths,
, was {1,2,4,8,16}. Section 2
described how a faster, but less flexible architecture could be obtained by
removing some of the capability of the L1 data mapping block. In this
section, we investigate the effects of changing the minimum effective
data width (smallest value of ). Intuitively, the
higher the minimum data width, the less flexible the L1 mapping block, and
hence, the less flexible the architecture.
Figure 7 shows how the minimum L1 data width affects
the average access time and area of each architecture for three values of
n (b is fixed at 64Kbits). As the graphs show,
removing switches from the
L1 mapping block has almost no effect on area; this isn't surprising, since
the switches are small and are controlled by a small number of programming
bits. The average access time, however, decreases noticeably as
switches are removed; the marked decrease at 16 is because if the
minimum output width is 16, then no L1 mapping block is needed at all.
Figure 8 shows that removing switches
has a devastating effect on flexibility.
Not only is the ``by 1''
configuration good for logical memories with width 1, but also for logical
memories with odd output widths (a 3-bit wide memory can be implemented
using 3 arrays in the ``by 1'' configuration). It is clear that the
decrease in delay as the minimum L1 mapping block output width is increased
does not make up for the loss in flexibility. Therefore, for this class of
architectures, all possible power of two widths should be included in
.