Cachgen - Automatic Cache Generation for Stratix FPGAs

Current Version: 1.0 -- July 3rd, 2003.
Created by: Peter Yiannacouras,

This software tool is cache generator which can produce caches with a variety of associativities, latencies, and dimensions. It is targetted at Altera FPGAs, specifically the Stratix FPGA, but may well work with other Altera devices.

To compile cachgen, type "make" under Unix.

To run cachegen execute 'cachegen' with no arguments to see Usage info. Note that data and address widths are given in bits and depth in words. Running 'make sample' will produce a sample cache in a directory called 'sample'.

Alternatively, you can use the script to generate all cache variants for a given dimension. For example 'sh 32 16 24 test' creates a 32 word deep cach with address width of 16 bits and data width of 24 bits. Type 'make samplegenall' for an example.

Cachegen is a combination of C code and parameterizable Verilog. It takes Cache parameters as input, and produces Altera-specific Verilog as output. Executables are available for Linux, and Solaris, and source code is provided for those who want to modify the code or for those who want to compile for other platforms.

Click here to download the source code, makefile and sample scripts for Cachegen

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