FPGA CAD Software From the Toronto FPGA Research Group

Hardware/Processor/Interconnect Core Generators

• GENIE: Automatic Synthesis of FPGA Interconnect
  
  
• VESPA: Vector Extended Soft Processor Architecture
  
  
• The Super Small Soft Processor
  
  
• SPREE: Soft Processor Rapid Exploration Environment
  
  
• Portable, Scalable FPGA Linear Equation Solver for Altera FPGAs
  
  
• Cachegen - Automatic Parameterized Cache Generation for Stratix FPGAs
  
  
• PSAC - A Variable Serial Data Width Arithmetic Module Generator .
  
  

Placement and Routing and Front End Synthesis for FPGAs

• The Verilog-to-Routing Project, VTR, including VPR 7
  • This is a world-wide collaborative project to create a next-generation FPGA CAD flow for architectur and CAD exploration. We would ultimately like to be a platform for the creation of FPGAs in the heterogenous Processor/Many Core/FPGA chips of the future, as well as development of next-generation FPGAs.
  • Front End Synthesis using ODIN II
  • Can now target far more complex logic blocks, described in a new version of the FPGA architecture description language.
  • Logic Synthesis using Berkeley's ABC
  • Integrated Packing, Placement and Routing Using VPR 6 Beta (area driven only)
  
  
• VPR and VPack Version 5.0: New Release of VPR
  • Single Driver Routing
  • Heterogeneous Logic (for placement and routing only, so far)
  • Optimized Architecture files across a wide range of architectures and processes and Area-Speed Tradeoffs
  • Regression Tests
  
  
• Odin - A Front-End Elaborator and Partial Mapper for Heterogenous FPGAs
  
  
• FPGA Placement and Routing Challenge!
  
  
• VPR and VPack Version 4.30 : Versatile Packing, Placement and Routing for FPGAs
  

Synthetic Digital Circuit Benchmark Generation and Characterization of Digital Circuits

• CCIRC and CGEN - Next Generation Synthetic Circuit Generation
  
  
• CIRC and GEN - Characterization and Quality Random Digital Circuit Generation

Hardware Description Language Synthesis for FPGAs

• Subset C Hardware Description Language and Compiler (C to XNF) - Transmogrifier C

Technology Mapping

• Chortle-Technology Mapping for Lookup Tables (ZIP File)

Graphics Package - Easy GL by Vaughn Betz and William Chow

• Easy GL Graphics Package for the PC .
  

EDIF to BLIF Converter

• EDIF to BLIF Converter.