Name | Years | Degree | Title of Research and Publications | Last Known Position |
Keith Redmond | 07- | M.A.Sc. | Multi-FPGA Systems | Degree in progress |
David Woods | 07- | M.A.Sc. | Multi-FPGA Systems | Degree in progress |
Danny Gupta | 07- | M.A.Sc. | Multi-FPGA Systems | Degree in progress |
Alex Kaganov | 06- | M.A.Sc. | FPGA Acceleration of Monte-Carlo Based Credit Derivative Pricing [19,20] | Degree in progress |
Daniel Nunes | 06- | M.A.Sc. | Performance Measurement in TMD-MPI [21,19] | Degree in progress |
Emanuel Ramalho | 06- | M.A.Sc. | Linpack on a Multi-FPGA Cluster [21,19] | Degree in progress |
Arun Patel | 04-07 | M.A.Sc. | A 3D Convolution Engine for Computing the Reciprocal-Space Ewald Electrostatic Energy in Molecular Dynamics Simulations [22,23,24,25,19] | Arches Computing Systems
Toronto, ON |
Manuel Saldaña | 04-06 | M.A.Sc. | A Parallel Programming Model for a Multi-FPGA Multiprocessor Machine [22,23,26,24,27,28,29,21,30,19] | Arches Computing Systems
Toronto, ON |
Chris Comis | 03-05 | M.A.Sc. | A High-Speed Inter-Process Communication Architecture for FPGA-Base Hardware Acceleration of Molecular Dynamics [31,24] | PMC Sierra
Burnaby, BC |
David Chui | 03-05 | M.A.Sc. | An FPGA Implementation of the Ewald Direct Space and Lennard-Jones Compute Engines [32] | ATI Technologies
Thornhill, ON |
Sam Lee | 03-05 | M.A.Sc. | An FPGA Implementation of the Smooth Particle Mesh Ewald Reciprocal Sum Compute Engine (RSCE) [33] | ATI Technologies
Thornhill, ON |
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Name | Years | Degree | Title of Research and Publications | Last Known Position |
Amy Wang | 99-01 | M.A.Sc. | Code Compaction for VLIW Instructions [34] | IBM, Toronto |
Lesley Shannon | 99-01 | M.A.Sc. | Impact of Intellectual Property Cores on Field Programmable Gate Array Designs [35] | Ph.D. candidate, UofT |
Humberto Rico | 98-00 | M.A.Sc. | HDL-Level Partitioning of Circuits [36] | Xilinx Toronto, ON |
Jorge Carrillo | 98-00 | M.A.Sc. | Evaluation of the OneChip Reconfigurable Processor [37,38] | Xilinx, San Jose, CA |
Scott Nunweiler | 98-99 | M.Eng. | A Case Study in Design for Reuse Using VHDL [39] | PMC Sierra |
Jianghong Hu | 97-00 | M.A.Sc. | A Datapath Compiler with Technology Portability [40] | ATI Technologies
Thornhill, ON |
Hsien-en Peng | 97-99 | M.A.Sc. | UTDSP: A VLIW Programmable DSP Processor [41] | CEO, Terasic Technologies, Inc. |
Tor Aamodt | 97-01 | M.A.Sc. | Compiler for Fixed-Point Processors [42,43,44,45,46] | Ph.D. candidate |
Jeff Jacob | 96-98 | M.A.Sc. | Memory Interfacing for Reconfigurable Processors [47,48] | CEVA, Israel |
Vineet Joshi | 96-98 | M.Eng. | ASIC Design Flow Development. This work was used by CMC as an aid to their design flow. [49] | |
Ralph Wittig | 93-95 | M.A.Sc. | OneChip: An FPGA Processor With Reconfigurable Logic [50,51] | Xilinx
San Jose, CA |
David Yeh | 92-95 | M.A.Sc. | A Multiprocessor Viterbi Decoder Using Xilinx FPGAs [52,53,54] | ATI Technologies
Thornhill, ON |
Mohamed El Ebiary | 92-94 | M.A.Sc. | History Guided Prefetching in a Telephone Switching Application [55] | Alcatel
Kanata, ON |
Robert Jeschke | 90-94 | M.A.Sc. | An FPGA Based Reconfigurable Coprocessor for the IBM PC [56] | Scientific Atlanta
Scarborough, ON |
Harpreet Singh Gill | 93-94 | M.A.Sc. | Improved Optimization Strategies for Blocked Algorithms [57] | Nortel
Toronto, ON |
Pok Yan Lee | 91-93 | M.Eng. | An FPGA Implementation of the DLX [58] | Nortel, Ottawa, ON |
Sushant Verman | 90-93 | M.A.Sc. | An FPGA-Based Reconfigurable Computing Array [59] | Cogency Technology
Toronto, ON |
Mazen Saghir | 91-93 | M.A.Sc. | Architectural and Compiler Support for DSP Applications [60,61] | Assistant Professor
American University of Beirut |
Vijaya Singh | 89-92 | M.A.Sc. | An Optimizing C Compiler for a General Purpose DSP Architecture [62] | IBM, Toronto |
Qing Zheng | 90-92 | M.A.Sc. | SEP: A General Purpose Object-Oriented Environment for Discrete-Event Simulations [63,64] | Entrisphere,
Santa Clara, CA |
Grant Goodes | 89-91 | M.A.Sc. | Stache: A Novel Cache Architecture Using Predictive Prefetch [65,66,67] | Cortina Systems
Kanata, ON |
Michael Takefman | 88-90 | M.A.Sc. | Improving the Performance of a DSP Microprocessor Architecture [68,69] | Cisco Systems
Kanata, ON |