Name | Years | Degree | Title of Research and Publications | Last Known Position |
Chris Madill | 06- | Ph.D. | Molecular Dynamics on a Multi-FPGA System with Prof. Régis Pomès | Degree in Progress |
Samir Parikh | 04-07 | M.A.Sc. | A CMOS Imager for DNA Detection with Prof. Gulak | Fujitsu, Sunnyvale, CA |
Keith Farkas | 92-97 | Ph.D. | Memory-System Design
Considerations for Dynamically- Scheduled Microprocessors (with Prof. Vranesic. ) [70,71,72,73,74,75] |
Hewlett Packard Labs,
Palo Alto, CA |
Dean D'Mello | 94-96 | M.A.Sc. | Synthesis of FPAA Cores Using an Intermediate
Layout Language Approach [76]
(with Prof. Gulak. ) |
Cadence Design Systems
(Canada) Ltd., Toronto, ON |
Gennady Feygin | 90-95 | Ph.D. | Arithmetic Coding: Algorithms and VLSI Architectures (with Prof. Gulak) [77,78,79,80] | Texas Instruments
Warren, NJ |
Paul Chow | 93-94 | M.A.Sc. | A Field-Programmable Mixed-
Analog-Digital Array (with Prof. Gulak) [81,82] |
ATI Technologies,
Thornhill, ON |
Soon Seo | 90-94 | M.A.Sc. | A High Speed Field-Programmable Gate Array Using Programmable Minitiles (with Prof. Rose) [83,84,85] | ATI Technologies
Thornhill, ON |
Satwant Singh | 89-91 | M.A.Sc. | The Effect of Logic Block Architecture on the Speed of Field-Programmable Gate Arrays (with Prof. Rose) [86,87,88,89,67] | Lattice Semiconductor
Corp., San Jose, CA |
Gennady Feygin | 88-90 | M.A.Sc. | A Multiprocessor Architecture for Viterbi Decoders with Linear Speed-up (with Prof. Gulak) [90,67,91,53] | Texas Instruments
Warren, NJ |