The VLIW model that we have been using as the target for our compiler was only intended to make the compilation task easy so that we could eliminate performance constraints imposed by the hardware. This allowed us to more easily develop the compiler technology. The model is not suitable for implementation because it would need a very high instruction bandwidth.
The next step is to investigate ways to achieve the desirable features
of a VLIW architecture, as viewed by the compiler, in a realizable
architecture[13].
We are currently implementing a version of our architecture in a
3-level metal TSMC process using the services of the
Canadian Microelectronics Corporation.
Some early work on this was presented by Sean Peng[14] at the
Symposium on Microelectronics Research & Development in Canada
(MR&DCAN'99)
and was awarded the
Canadian Microelectronics Corporation (CMC) International Travel Award
(CMC Award).
With the growing interest in multimedia, which is a large application area for DSPs, we have started to investigate some new areas. The introduction by Intel of their MMX processors, and processors from other companies using similar approaches, has presented a new optimization problem to the compilation of efficient programs because of the new short vector extension instructions. We are also examining the feasibility of using vector processor technology for multimedia applications as a way of achieving a high degree of processor parallelism, without the complexity of modern processors. More about this work can be seen at http://www.eecg.toronto.edu/~corinna/vector/index.html.